From: Michael McNamara (mac@surefirev.com)
Date: Tue Nov 30 1999 - 14:32:44 PST
Clifford E. Cummings writes:
> [1 <text/plain; us-ascii (7bit)>]
> VSG -
>
> I am making last-minute updates to the Verilog Annex A BNF.
>
> The updates include the capability to make assignments within declarations
> for all of the register types except event, per my e-mail from last week.
>
> Mike Baird has also pointed out that it is possible to change delays during
> runtime. I have tried this on procedural assignment delays, continuous
> assignment delays and gate-primitive delays, using Verilog-XL and VCS. It
> works. I was surprised! The current BNF does not permit reassignment of
> delays during runtime.
>
What in the BNF prevents reassignment of delays during runtime?
I see (in the draft 3 PDF file)
blocking_assignment ::= reg_lvalue [ delay_or_event_control ] expression
delay_or_event_control ::= delay_control
| event_control
| repeat ( expression ) event_control
delay_control ::= # delay_value
| ( mintypmax_expression )
mintypmax_expression ::= expression
| expression : expression : expression
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