From: Adam Krolnik (krolnik@lsil.com)
Date: Tue Dec 28 1999 - 09:28:34 PST
Good morning all:
Page 183, Section 12-6 second paragraph, third sentence says:
Once a name is defined in a port declaration it shall not be
defined again with the same type or another type."
Shalom asks:
The third sentence is not clear. What does "shall not be defined again"
mean ? Does it mean "shall not be defined again" in another port
declaration or does it mean something else ?
<p>Proposed:
Once a name is defined in a port declaration with a type, it shall not
be defined again in another port declaration.
Proposed change:
Clarify the intent of the third sentence to disallow multiple port
declarations for the same name.
E.g.
input aport; // First declaration - okay.
input aport; // Error - multiple declaration
output aport; // Error - multiple declaration and different type.
---------------------------------------------------------------------
Section 12.3.6 Connection module instance ports by name. pg 186
Was:
The port expression can be any valid expression using identifiers
in the scope of the instantiating module:
A simple identifier
A bit-select of a vector declared within the module.
A part-select of a vector declarated within the module.
Any combination of the above.
Proposed:
The port expression can be any valid expression.
A simple identifier
A hierarchical identifier.
A bit select of a vector.
A part select of a vector.
Any combination of the above.
Proposed change:
Hierarchical identifiers can be used as port expressions?!
Why not?! XL allows it, VCS disallows it.
----------------------------------------------------------------
There is no text concerning multiple module instance port
connections (by name.) What should be occurring here?
Errors? XL says error, VCS says okay.
module test;
a ia (.i (a), .i (b), // connect input port twice.
.o (c), .o (d), // connect output port twice.
.e (e), .e (f)); // connect inout port twice.
endmodule
module a(i, o, e);
input i;
output o;
inout e;
endmodule
There is also no text discussing:
module b(a, a);
...
XL says okay, VCS says warning - result is oring for inputs.
<p><p> Adam Krolnik
Verification Mgr.
LSI Logic Inc.
Plano TX. 75074
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