From: Steven Sharp (sharp@cadence.com)
Date: Wed Jan 19 2000 - 12:33:29 PST
I have verified that it is not legal to mix net declarations that have
assignments with ones that do not in the same declaration in Verilog-XL.
I have also verified that it is legal to assign a trireg net a value in
the declaration. I don't think that there is a problem with this aside
from the inability to declare a drive strength in that situation (which
is probably to avoid confusion with declaring the capacitive strength
of the trireg).
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