From: Tom Fitzpatrick (tfitz@cadence.com)
Date: Tue Jan 25 2000 - 12:17:27 PST
Hi Cliff,
If attributes were left off certain statements, then it was simply an
oversight on my part. Attributes should be specifyable for any statement.
-Fitz
At 09:37 AM 1/24/00 -0800, Clifford E. Cummings wrote:
>Tom & Steve -
>
>Adam has pointed out missing attributes from important statements. Could
>you quickly tell us if attributes should be added to the following:
>
>[Note, no real, realtime, event or genvar declarations.]
>[Note, no looping statements]
>Within a function body??
>
>We are not sure if attributes are consistent in the LRM. If you could get
>back to us quickly with an answer, we will add them; otherwise, it might be
>wise to pull them out of the Verilog-2000 spec until they are more
>consistently added to the BNF.
>
>- Cliff
>
>===========
>
>Section 2.8 Attributes
>
>Was:
>
>See the syntax at the end of this section for a list of statements that
>may have attributes attached to them.
>
>Proposed:
>
>See the syntax box ... ?!
>
>Syntax 2-3 Statements with attributes attached.
>
>module declarations
>module or generate item
>inout declaration
>input declaration
>output declaration
>integer declaration
>net declaration
>reg declaration
>time declaration
>[ Note, no real, realtime, event or genvar declarations.]
>function declaration
>task declaration
>block reg declaration
>gate instantiation
>module instantiation
>ordered port connection
>named port connection
>udp declaration
>udp output declaration
>udp input declaration
>initial construct
>always construct
>par(allel) block
>seq(ential) block
>conditional statement
>if else if statement
>case statement
>[Note, no looping statements]
>task call
>function call
>unary operator
>binary operator
>conditional operator
>
>Proposed change:
>Add missing table referred to in the text.
>
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>// Cliff Cummings E-mail: cliffc@sunburst-design.com //
>// Sunburst Design, Inc. Phone: 503-579-6362 / FAX: 503-579-7631 //
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