Re: Verilog 2000 attributes

From: Steven Sharp (sharp@cadence.com)
Date: Wed Feb 09 2000 - 17:59:40 PST


Adam,

All of the ambiguities for statements arise from the placement of attributes
in positions inside the control statements. These positions were originally
chosen for compatibility with OVI attributes. It would be easier to implement
attributes if we could just modify the support for OVI attributes slightly.

However, since this is causing problems, we are willing to support doing the
right thing. Changing the positions of attributes to be consistent and avoid
these problems would be best in the longer term. This would require changing
the BNF and the text about attributes.

It looks to me like the best approach is to allow attributes on any statement
and to put it in a consistent place, like at the beginning. This would be
replace allowing attributes to be statements. This would resolve all of the
ambiguities involving control statements. I can see where it might be
important to be able to attach an attribute to an "always" or "initial" block
also (e.g. to give information about latch inference for an "always" block).
This could be done by allowing an attribute before the "always" or "initial"
keyword. Something similar should be possible for continuous assignments,
though I'm not sure about ones that are part of net declarations.



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