From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Feb 10 2000 - 02:08:15 PST
Stu's original e-mail should be implemented almost verbatim. A few changes
were made to his message and should be voted on as shown below.
See Stu's original e-mail dated 1/18/00 for pretty colors.
Regards - Cliff
------------------
The 1364-1995 LRM used a mixture of terms to describe the reg, integer,
time, real and realtime data types, such as "registers", "variables", and
"register variables". A change was approved to eliminate the confusing
"register" term in the LRM, and consistently refer to these data types as
either "variables" to indicate the entire class, or "reg" to refer to just
that specific data type.
The implementation of the change was not complete, plus, in many places, a
global search and replace used the term "reg" "register", when "variable"
should have been used (to indicate the full class of data types).
Here are the hundred or so places I found that need to be changed...
Stu
<p>------------------
Annex A:
**** THE BNF HAS BEEN APPROPRIATELY UPDATED ****
------------------
Introduction, 3rd paragraph:
DRAFT 4:
Verilog contains a rich set of built-in primitives, including logic gates,
user-definable primitives, switches, and wired logic. It also has device
pin-to-pin delays and timing checks. The mixing of abstract levels is
essentially provided by the semantics of two data types: nets and
registers. Continuous assignments, in which expressions of both registers
and nets can continuously drive values onto nets, provide the basic
structural construct. Procedural assignments, in which the results of
calculations involving register and net values can be stored into
registers, provide the basic behavioral construct. A design consists of a
set of modules, each of which has an I/O interface, and a description of
its function, which can be structural, behavioral, or a mix. These modules
are formed into a hierarchy and are interconnected with nets.
CHANGE TO:
Verilog contains a rich set of built-in primitives, including logic gates,
user-definable primitives, switches, and wired logic. It also has device
pin-to-pin delays and timing checks. The mixing of abstract levels is
essentially provided by the semantics of two data types: nets and
variables. Continuous assignments, in which expressions of both variables
and nets can continuously drive values onto nets, provide the basic
structural construct. Procedural assignments, in which the results of
calculations involving variable and net values can be stored into
variables, provide the basic behavioral construct. A design consists of a
set of modules, each of which has an I/O interface, and a description of
its function, which can be structural, behavioral, or a mix. These modules
are formed into a hierarchy and are interconnected with nets.
------------------
Section 1.4, Item 3, Data types:
DRAFT 4:
This section describes net and reg data types...
CHANGE TO:
This section describes net and variable data types...
------------------
Section 3.2, title and first paragraph:
DRAFT 4:
3.2 Nets and regs
There are two main groups of data types: the reg data types and the net
data types...
CHANGE TO:
3.2 Nets and variables
There are two main groups of data types: the variables data types and the
net data types...
------------------
Section 3.2.1, 1st paragraph, last sentence:
DRAFT 4:
It is illegal to redeclare a name already declared by a net, parameter or
reg declaration.
CHANGE TO:
It is illegal to redeclare a name already declared by a net, parameter or
variable declaration.
------------------
Section 3.2.2, title and first 4 paragraphs:
DRAFT 4:
3.2.2 reg declarations
A reg is an abstraction of a data storage element. A reg shall store a
value from one assignment to the next. An assignment statement in a
procedure acts as a trigger that changes the value in the data storage
element. The initialization value for reg, time, and integer data types
shall be the unknown value, x. The default initialization value for a reg
data type shall be the unknown value, x. The default initialization value
for real and realtime reg datatypes shall be 0.0. If a reg declaration
assignment, see 6.2.1, is used the reg shall take this value as if the
assignment occurred in a blocking assignment in an initial construct. It
is illegal to redeclare a name already declared by a net, parameter, or reg
declaration.
NOTE-In previous versions of the Verilog standard, the term register was
used to encompass both the reg and variable types; but that the term is no
longer used as a Verilog data type.
The syntax for reg declarations is given in Syntax 3-2.
[syntax 3-2 box]
If a set of nets or regs share the same characteristics, they can be
declared in the same declaration statement.
CHANGE TO:
3.2.2 variable declarations
A variable is an abstraction of a data storage element. A variable shall
store a value from one assignment to the next. An assignment statement in a
procedure acts as a trigger that changes the value in the data storage
element. The initialization value for reg, time, and integer data types
shall be the unknown value, x. [Strike the following sentence; it is
redundant with the previous sentence]The default initialization value for a
reg data type shall be the unknown value, x. The default initialization
value for real and realtime variable datatypes shall be 0.0. If a variable
declaration assignment, see 6.2.1, is used, the variable shall take this
value as if the assignment occurred in a blocking assignment in an initial
construct. It is illegal to redeclare a name already declared by a net,
parameter, or variable declaration.
NOTE-In previous versions of the Verilog standard, the term register was
used to encompass both the reg, integer, time, real and realtime types; but
that the term is no longer used as a Verilog data type.
The syntax for variable declarations is given in Syntax 3-2.
[syntax 3-2 box]
If a set of nets or variables share the same characteristics, they can be
declared in the same declaration statement.
------------------
Section 3.2.2, Syntax 3-2 title:
DRAFT 4:
Syntax for reg declaration
CHANGE TO:
Syntax for variable declaration
------------------
Section 3.2.2, Caution box after last paragraph:
DRAFT 4:
Regs can be assigned negative values, but only signed, integer, real, and
realtime shall retain the significance of the sign...
CHANGE TO:
Variables can be assigned negative values, but only signed regs, integer,
real, and realtime variables shall retain the significance of the sign...
------------------
Section 3.5, 1st paragraph:
DRAFT 4:
The syntax shown in 3.2 shall be used to declare nets and regs explicitly...
CHANGE TO:
The syntax shown in 3.2 shall be used to declare nets and variables
explicitly...
------------------
Section 3.9, 1st paragraph:
DRAFT 4:
In addition to modeling hardware, there are other uses for regs in an HDL
model...
CHANGE TO:
In addition to modeling hardware, there are other uses for variables in an
HDL model...
------------------
Section 3.9, 5th paragraph after Syntax 3-3 box:
DRAFT 4:
The time variables shall behave the same as a register of at least 64 bits...
CHANGE TO:
The time variables shall behave the same as a reg of at least 64 bits...
------------------
Section 3.9, 6th paragraph after Syntax 3-3 box, 2nd sentence:
DRAFT 4:
...Except for the following restrictions, regs declared as real can be used
in the same places that integers and time variables are used:
CHANGE TO:
...Except for the following restrictions, variables declared as real can be
used in the same places that integer and time variables are used:
------------------
Section 3.9.2, 2nd paragraph:
DRAFT 4:
Implicit conversion shall take place when an expression is assigned to a
real. Individual bits that are x or z in the net or the reg shall be
treated as zero upon conversion.
CHANGE TO:
Implicit conversion shall take place when an expression is assigned to a
real. Individual bits that are x or z in the net or the variable shall be
treated as zero upon conversion.
------------------
Section 3.10, 1st paragraph:
DRAFT 4:
An array declaration for a net or a reg declares an element type which is
either scalar or vector (see 3.3). For example:
CHANGE TO:
An array declaration for a net or a variable declares an element type which
is either scalar or vector (see 3.3). For example:
------------------
Section 3.10, 3rd paragraph (including the note), 4th sentence:
DRAFT 4:
...See 3.2.1 and 3.2.2 for net and reg declarations...
CHANGE TO:
...See 3.2.1 and 3.2.2 for net and variable declarations...
------------------
Section 3.10, 5th paragraph, 5th sentence:
DRAFT 4:
...This option provides a mechanism to reference different array elements
depending on the value of other regs and nets in the circuit...
CHANGE TO:
...This option provides a mechanism to reference different array elements
depending on the value of other variables and nets in the circuit...
------------------
Section 3.10.3, 2nd paragraph, 3rd sentence:
DRAFT 4:
...This option provides a mechanism to reference different memory words,
depending on the value of other regs and nets in the circuit...
CHANGE TO:
...This option provides a mechanism to reference different memory words,
depending on the value of other variables and nets in the circuit...
------------------
Section 3.10.3, Numbering change:
DRAFT 4:
**** BTF voted for NO CHANGE *****
------------------
Section 3.10.3.1.2, Note paragraph:
DRAFT 4:
NOTE-Implementations may limit the maximum size of a reg array, but they
will at least be 16777216 (224).
CHANGE TO:
NOTE-Implementations may limit the maximum size of an array, but they shall
at least be 16777216 (224).
------------------
Section 3.11, 1st paragraph:
DRAFT 4:
Verilog HDL parameters do not belong to either the reg or the net group.
Parameters are not variables, they are constants. There are two types of
parameters: module parameters and specify parameters. It is illegal to
redeclare a name already declared by a net, parameter or reg declaration.
CHANGE TO:
Verilog HDL parameters do not belong to either the variable or the net
group. Parameters are not variables, they are constants. There are two
types of parameters: module parameters and specify parameters. It is
illegal to redeclare a name already declared by a net, parameter or
variable declaration.
------------------
Section 3.12, 4th and 5th paragraph:
DRAFT 4:
The block name space is introduced by the named block (see 9.8), function
(see 10.3), and task (see 10.2) constructs. It unifies the definitions of
the named blocks, functions, tasks, and the reg type of declaration (see
3.2.2). The reg type of declaration includes the reg, integer, time, real,
realtime, event, and parameter declarations.
The module name space is introduced by the module, macromodule, and
primitive constructs. It unifies the definition of functions, tasks, named
blocks, instance names, net type of declaration, and reg type of
declaration. The net type of declaration includes wire, wor, wand, tri,
trior, triand, tri0, tri1, trireg, supply0, and supply1 (see 3.7).
CHANGE TO:
The block name space is introduced by the named block (see 9.8), function
(see 10.3), and task (see 10.2) constructs. It unifies the definitions of
the named blocks, functions, tasks, parameters, named events and the
variable type of declaration (see 3.2.2). The variable type of declaration
includes the reg, integer, time, real and realtime declarations.
The module name space is introduced by the module, macromodule, and
primitive constructs. It unifies the definition of functions, tasks, named
blocks, instance names, parameters, named events, net type of declaration,
and variable type of declaration. The net type of declaration includes
wire, wor, wand, tri, trior, triand, tri0, tri1, trireg, supply0, and
supply1 (see 3.7).
------------------
Section 3.12, 6th paragraph, last sentence:
DRAFT 4:
A port name introduced in the port name space may be reintroduced in the
module name space by declaring a reg or a wire with the same name as the
port name.
CHANGE TO:
A port name introduced in the port name space may be reintroduced in the
module name space by declaring a variable or a wire with the same name as
the port name.
------------------
Section 4, Intro section, 6th paragraph, 3rd bullet:
DRAFT 4:
- Register variables of type reg, integer, time, real, and realtime
CHANGE TO:
- Variables of type reg, integer, time, real, and realtime
------------------
Section 4.1.6, 1st paragraph:
DRAFT 4:
An arithmetic operation on a reg type register shall be treated differently
than an arithmetic operation on an integer data type. A reg data type shall
be treated as an unsigned value and an integer data type shall be treated
as a signed value. Thus, if a sized constant with a negative value is
stored in a reg type register, a positive constant, which is a 2's
complement of the sized constant, shall be the value stored in the reg type
register. When this reg is used in an arithmetic expression, the positive
constant shall be used as the value of the reg. In contrast, if a sized
constant with a negative value is stored in an integer type variable and
used in an arithmetic expression, the expression shall evaluate using
signed arithmetic.
CHANGE TO:
An arithmetic operation on a reg type variable shall be treated differently
than an arithmetic operation on an integer data type. A reg data type shall
be treated as an unsigned value and an integer data type shall be treated
as a signed value. Thus, if a sized constant with a negative value is
stored in a reg type variable, a positive constant, which is a 2's
complement of the sized constant, shall be the value stored in the reg type
variable. When this reg is used in an arithmetic expression, the positive
constant shall be used as the value of the reg. In contrast, if a sized
constant with a negative value is stored in an integer type variable and
used in an arithmetic expression, the expression shall evaluate using
signed arithmetic.
------------------
Section 4.2, 1st and 2nd paragraphs:
DRAFT 4:
There are several types of operands that can be specified in expressions.
The simplest type is a reference to a net or reg in its complete form-that
is, just the name of the net or reg is given. In this case, all of the bits
making up the net or reg value shall be used as the operand.
If a single bit of a vector net or reg is required, then a bit-select
operand shall be used. A part-select operand shall be used to reference a
group of adjacent bits in a vector net or reg.
CHANGE TO:
There are several types of operands that can be specified in expressions.
The simplest type is a reference to a net or variable in its complete
form-that is, just the name of the net or variable is given. In this case,
all of the bits making up the net or variable value shall be used as the
operand.
If a single bit of a vector net, reg variable, integer variable or time
variable is required, then a bit-select operand shall be used. A
part-select operand shall be used to reference a group of adjacent bits in
a vector net, vector reg, integer variable or time variable.
------------------
Section 4.2.1, title, 1st and 2nd paragraphs:
DRAFT 4:
4.2.1 Net and reg bit-select and part-select addressing
Bit-selects extract a particular bit from a vector net or reg. The bit can
be addressed using an expression. If the bit-select is out of the address
bounds or the bit-select is x or z, then the value returned by the
reference shall be x.
Several contiguous bits in a vector reg or net can be addressed and are
known as part-selects. There are two types of part-selects, a constant
part-select and an indexed part-select. A constant part-select of a vector
reg or net is given with the following syntax.:
CHANGE TO:
4.2.1 Vector bit-select and part-select addressing
Bit-selects extract a particular bit from a vector net, vector reg, integer
variable or time variable. The bit can be addressed using an expression. If
the bit-select is out of the address bounds or the bit-select is x or z,
then the value returned by the reference shall be x.
Several contiguous bits in a vector net, vector reg, integer variable or
time variable can be addressed and are known as part-selects. There are two
types of part-selects, a constant part-select and an indexed part-select. A
constant part-select of a vector is given with the following syntax:
------------------
Section 4.2.1, 4th and 5th paragraphs:
DRAFT 4:
The bit-select or part-select of a reg declared as real or realtime shall
be considered illegal.
An indexed part select of a vector reg or net is given with the following
syntax:
CHANGE TO:
The bit-select or part-select of a variable declared as real or realtime
shall be considered illegal.
An indexed part select of a vector net, vector reg, integer variable or
time variable is given with the following syntax:
------------------
Section 4.2.1, 6th paragraph, 7th sentence:
DRAFT 4:
...Part-selects that address a range of bits that are completely out of the
address bounds of the net or reg, ...
CHANGE TO:
...Part-selects that address a range of bits that are completely out of the
address bounds of the net, reg, integer or time, ...
------------------
Section 4.4.3, 1st line of example:
DRAFT 4:
CHANGE TO:
The first reg declaration should be indented to line up with the subsequent
declarations.
------------------
Section 5.2, 3rd paragraph:
DRAFT 4:
Every change in value of a net or reg in the circuit being simulated, as
well as the named event, is considered an update event.
CHANGE TO:
Every change in value of a net or variable in the circuit being simulated,
as well as the named event, is considered an update event.
------------------
Section 6, 1st paragraph and bullets:
DRAFT 4:
The assignment is the basic mechanism for placing values into nets and
regs. There are two basic forms of assignments:
-The continuous assignment, which assigns values to nets
-The procedural assignment, which assigns values to regs
CHANGE TO:
The assignment is the basic mechanism for placing values into nets and
variables. There are two basic forms of assignments:
-The continuous assignment, which assigns values to nets
-The procedural assignment, which assigns values to variables
------------------
Section 6, Table 6-1, Left-hand side of procedural assignments:
DRAFT 4:
reg (vector or scalar)
Bit-select of a vector reg
Constant part select of a vector reg
Memory word
Indexed part select of a vector reg
Concatenation of any of the above five LHS
CHANGE TO:
variables (vector or scalar)
Bit-select of a vector reg, integer or time variable
Constant part select of a vector reg, integer or time variable
Memory word
Indexed part select of a vector reg, integer or time variable
Concatenation of regs, or bit or part selects of regs
------------------
Section 6.2, 2nd paragraph:
DRAFT 4:
As stated in 6.1, continuous assignments drive nets in a manner similar to
the way gates drive nets. The expression on the right-hand side can be
thought of as a combinatorial circuit that drives the net continuously. In
contrast, procedural assignments put values in regs. The assignment does
not have duration; instead, the reg holds the value of the assignment until
the next procedural assignment to that reg.
CHANGE TO:
As stated in 6.1, continuous assignments drive nets in a manner similar to
the way gates drive nets. The expression on the right-hand side can be
thought of as a combinatorial circuit that drives the net continuously. In
contrast, procedural assignments put values in variables. The assignment
does not have duration; instead, the variable holds the value of the
assignment until the next procedural assignment to that variable.
------------------
Section 6.2.1, Title and 1st paragraph:
DRAFT 4:
6.2.1 reg declaration statement
Register declaration assignments are special cases of procedural
assignments as they assign values to declarations of integer, real,
realtime, reg and time variables. Register declaration assignments allow an
initial value to be made in the same statement which declares integer,
real, realtime, reg and time variables. The assignment shall be a constant
expression. The assignment does not have duration; instead, the register
variables hold values until the next assignment to the individual register
variables. Register declaration assignments to arrays are not allowed.
CHANGE TO:
6.2.1 Variable declaration assignment
Variable declaration assignments are special cases of procedural
assignments as they assign values to declarations of integer, real,
realtime, reg and time variables. Variable declaration assignments allow an
initial value to be made in the same statement which declares integer,
real, realtime, reg and time variables. The assignment shall be a constant
expression. The assignment does not have duration; instead, the variables
hold values until the next assignment to the individual variables. Variable
declaration assignments to arrays are not allowed.
------------------
Section 6.2.1, last paragraph:
DRAFT 4:
NOTE-If the same register variable is assigned different values both in an
initial block and in a register variable declaration assignment, the order
of the evaluation is undefined.
CHANGE TO:
NOTE-If the same variable is assigned different values both in an initial
block and in a variable declaration assignment, the order of the evaluation
is undefined.
------------------
Section 6.2.2, Title and 1st paragraph:
DRAFT 4:
6.2.2 Reg declaration syntax
The syntax for reg declaration assignments is given in Syntax 6-2.
CHANGE TO:
6.2.2 Variable declaration syntax
The syntax for variable declaration assignments is given in Syntax 6-2.
------------------
Section 9.2, 1st paragraph, second bullet:
DRAFT 4:
Procedural assignments update the value of regs under the control of the
procedural flow constructs that surround them.
CHANGE TO:
Procedural assignments update the value of variables under the control of
the procedural flow constructs that surround them.
------------------
Section 9.2, 2nd paragraph and bullets:
DRAFT 4:
The right-hand side of a procedural assignment can be any expression that
evaluates to a value. The left-hand side shall be a reg that receives the
assignment from the right-hand side. The left-hand side of a procedural
assignment can take one of the following forms:
- reg, integer, real, realtime, or time reg data type: an assignment to the
name reference of one of these data types.
- Bit-select of a reg, integer, or time reg data type: an assignment to a
single bit that leaves the other bits untouched.
- Part-select of a reg, integer, or time reg data type: a part-select of
one or more contiguous bits that leaves the rest of the bits untouched.
CHANGE TO:
The right-hand side of a procedural assignment can be any expression that
evaluates to a value. The left-hand side shall be a variable that receives
the assignment from the right-hand side. The left-hand side of a procedural
assignment can take one of the following forms:
- reg, integer, real, realtime, or time data type: an assignment to the
name reference of one of these data types.
- Bit-select of a reg, integer, or time data type: an assignment to a
single bit that leaves the other bits untouched.
- Part-select of a reg, integer, or time data type: a part-select of one or
more contiguous bits that leaves the rest of the bits untouched.
------------------
Section 9.2.1, 3rd paragraph (just after Syntax 9-1 box):
DRAFT 4:
In this syntax, reg_lvalue is a data type that is valid for a procedural
assignment statement, = is the assignment operator, and
delay_or_event_control is the optional intra-assignment timing control. The
control can be either a delay control (e.g., #6) or an event_control (e.g.,
@(posedge clk)). The expression is the right-hand side value that shall be
assigned to the left-hand side. If reg_lvalue requires an evaluation, it
shall be evaluated at the time specified by the intra-assignment timing
control.
CHANGE TO:
Change "reg_lvalue" to match the final BNF terminology (variable_lvalue).
------------------
Section 9.2.2, 1st paragraph:
DRAFT 4:
The nonblocking procedural assignment allows assignment scheduling without
blocking the procedural flow. The nonblocking procedural assignment
statement can be used whenever several reg assignments within the same time
step can be made without regard to order or dependence upon each other.
CHANGE TO:
The nonblocking procedural assignment allows assignment scheduling without
blocking the procedural flow. The nonblocking procedural assignment
statement can be used whenever several variable assignments within the same
time step can be made without regard to order or dependence upon each other.
------------------
Section 9.2.3, 3rd paragraph (just after Syntax 9-2 box):
DRAFT 4:
In this syntax, reg_lvalue is a data type that is valid for a procedural
assignment statement, <= is the nonblocking assignment operator, and
delay_or_event_control is the optional intra-assignment timing control. If
reg_lvalue requires an evaluation, it shall be evaluated at the same time
as the expression on the right-hand side. The order of evaluation of the
reg_lvalue and the expression on the right-hand side is undefined if timing
control is not specified.
CHANGE TO:
Change "reg_lvalue" to match the final BNF terminology (variable_lvalue).
------------------
Section 9.2.2, 1st paragraph after Example 3:
DRAFT 4:
When multiple nonblocking assignments are scheduled to occur in the same
reg in a particular time slot, the order in which the assignments are
evaluated is not guaranteed--the final value of the reg is indeterminate.
As shown in the following example, the value of reg a is not known until
the end of time step 4.
CHANGE TO:
When multiple nonblocking assignments are scheduled to occur in the same
variable in a particular time slot, the order in which the assignments are
evaluated is not guaranteed--the final value of the variable is
indeterminate. As shown in the following example, the value of reg a is not
known until the end of time step 4.
------------------
Section 9.2.2, 1st paragraph after Example 4:
DRAFT 4:
If the simulator executes two procedural blocks concurrently, and if these
procedural blocks contain nonblocking assignment operators to the same reg,
the final value of that reg is indeterminate. For example, the value of reg
a is indeterminate in the following example.
CHANGE TO:
If the simulator executes two procedural blocks concurrently, and if these
procedural blocks contain nonblocking assignment operators to the same
variable, the final value of that variable is indeterminate. For example,
the value of reg a is indeterminate in the following example.
------------------
Section 9.2.2, 1st paragraph after Example 5:
DRAFT 4:
When multiple nonblocking assignments with timing controls are made to the
same reg, the assignments are made without cancelling nonblocking
assignments scheduled at other times. Scheduling an assignment to a reg at
the same time as a previously scheduled assignment to the same reg shall
result in an arbitrary order of assignment to that reg, and, hence, the
final value of that reg cannot be predicted.
CHANGE TO:
When multiple nonblocking assignments with timing controls are made to the
same variable, the assignments are made without cancelling nonblocking
assignments scheduled at other times. Scheduling an assignment to a
variable at the same time as a previously scheduled assignment to the same
variable shall result in an arbitrary order of assignment to that variable,
and, hence, the final value of that variable cannot be predicted.
------------------
Section 9.3, 1st paragraph:
DRAFT 4:
The procedural continuous assignments (using keywords assign and force) are
procedural statements that allow expressions to be driven continuously onto
regs or nets. The syntax for these statements is given in Syntax 9-3.
CHANGE TO:
The procedural continuous assignments (using keywords assign and force) are
procedural statements that allow expressions to be driven continuously onto
variables or nets. The syntax for these statements is given in Syntax 9-3.
------------------
Section 9.3, last 2 paragraphs, after Syntax 9-3:
DRAFT 4:
The left-hand side of the assignment in the assign statement shall be a reg
reference or a concatenation of regs. It shall not be a memory word (array
reference) or a bit-select or a part-select of a reg.
In contrast, the left-hand side of the assignment in the force statement
can be a reg reference or a net reference. It can be a concatenation of any
of the above. Bit-selects and part-selects of vector regs or vector nets
are not allowed.
CHANGE TO:
The left-hand side of the assignment in the assign statement shall be a
variable reference or a concatenation of variables. It shall not be a
memory word (array reference) or a bit-select or a part-select of a variable.
In contrast, the left-hand side of the assignment in the force statement
can be a variable reference or a net reference. It can be a concatenation
of any of the above. Bit-selects and part-selects of vector variables or
vector nets are not allowed.
------------------
Section 9.3.1, 1st and 2nd paragraphs:
DRAFT 4:
The assign procedural continuous assignment statement shall override all
procedural assignments to a reg. The deassign procedural statement shall
end a procedural continuous assignment to a reg. The value of the reg shall
remain the same until the reg is assigned a new value through a procedural
assignment or a procedural continuous assignment. The assign and deassign
procedural statements allow, for example, modeling of asynchronous
clear/preset on a D-type edge-triggered flip-flop, where the clock is
inhibited when the clear or preset is active.
If the keyword assign is applied to a reg for which there is already a
procedural continuous assignment, then this new procedural continuous
assignment shall deassign the reg before making the new procedural
continuous assignment.
CHANGE TO:
The assign procedural continuous assignment statement shall override all
procedural assignments to a variable. The deassign procedural statement
shall end a procedural continuous assignment to a variable. The value of
the variable shall remain the same until the variable is assigned a new
value through a procedural assignment or a procedural continuous
assignment. The assign and deassign procedural statements allow, for
example, modeling of asynchronous clear/preset on a D-type edge-triggered
flip-flop, where the clock is inhibited when the clear or preset is active.
If the keyword assign is applied to a variable for which there is already a
procedural continuous assignment, then this new procedural continuous
assignment shall deassign the variable before making the new procedural
continuous assignment.
------------------
Section 9.3.2, 1st, 2nd and 4th paragraphs:
DRAFT 4:
Another form of procedural continuous assignment is provided by the force
and release procedural statements. These statements have a similar effect
to the assign-deassign pair, but a force can be applied to nets as well as
to regs. The left-hand side of the assignment can be a reg, a net, a
constant bit-select of a vector net, a part-select of a vector net, or a
concatenation. It cannot be a memory word (array reference) or a bit-select
or a part-select of a vector reg.
A force statement to a reg shall override a procedural assignment or
procedural continuous assignment that takes place on the reg until a
release procedural statement is executed on the reg. After the release
procedural statement is executed, the reg shall not immediately change
value (as would a net that is forced). The value specified in the force
statement shall be maintained in the reg until the next procedural
assignment takes place, except in the case where a procedural continuous
assignment is active on the reg.
A force procedural statement on a net overrides all drivers of the net-gate
outputs, module outputs, and continuous assignments-until a release
procedural statement is executed on the net.
Releasing a reg that currently has an active procedural continuous
assignment shall re-establish that assignment.
CHANGE TO:
Another form of procedural continuous assignment is provided by the force
and release procedural statements. These statements have a similar effect
to the assign-deassign pair, but a force can be applied to nets as well as
to variables. The left-hand side of the assignment can be a variable, a
net, a constant bit-select of a vector net, a part-select of a vector net,
or a concatenation. It cannot be a memory word (array reference) or a
bit-select or a part-select of a vector variable.
A force statement to a variable shall override a procedural assignment or
procedural continuous assignment that takes place on the variable until a
release procedural statement is executed on the variable. After the release
procedural statement is executed, the variable shall not immediately change
value (as would a net that is forced). The value specified in the force
statement shall be maintained in the variable until the next procedural
assignment takes place, except in the case where a procedural continuous
assignment is active on the variable.
A force procedural statement on a net overrides all drivers of the net-gate
outputs, module outputs, and continuous assignments-until a release
procedural statement is executed on the net.
Releasing a variable that currently has an active procedural continuous
assignment shall re-establish that assignment.
------------------
Section 9.6, for-loop description, paragraphs a and c:
DRAFT 4:
a. Executes an assignment normally used to initialize a reg that controls
the number of loops executed.
...
c. Executes an assignment normally used to modify the value of the
loop-control reg, then repeats step b.
CHANGE TO:
a. Executes an assignment normally used to initialize a variable that
controls the number of loops executed.
...
c. Executes an assignment normally used to modify the value of the
loop-control variable, then repeats step b.
------------------
Section 9.7, 2nd paragraph, 2nd sentence:
DRAFT 4:
...A simulation event can be a change of value on a net or reg ...
CHANGE TO:
...A simulation event can be a change of value on a net or variable ...
------------------
Section 9.7.2, 1st paragraph, 1st and 2nd sentences:
DRAFT 4:
The execution of a procedural statement can be synchronized with a value
change on a net or reg or the occurrence of a declared event. The value
changes on nets and regs can be used as events to trigger the execution of
a statement...
CHANGE TO:
The execution of a procedural statement can be synchronized with a value
change on a net or variable or the occurrence of a declared event. The
value changes on nets and variable can be used as events to trigger the
execution of a statement...
------------------
Section 9.7.3X, 1st paragraph, 1st sentence:
DRAFT 4:
A new data type, in addition to net and reg, called "event" can be
declared...
CHANGE TO:
A new data type, in addition to nets and variables, called "event" can be
declared...
------------------
Section 9.7.5, 1st, 2nd and 3rd paragraph:
DRAFT 4:
The event_expression list of an event control is a common source of bugs in
rtl simulations. Users tend to forget to add some of the nets or regs read
in the timing control statement. This is often found when comparing rtl
and gate level versions of a design. The implicit event_expression, @*, is
a convenient shorthand that eliminates these problems by adding all nets
and regs which are read by the statement (which can be a statement group)
of a procedural_timing_control_statement to the event_expression.
All net and reg identifiers which appear in the statement will be
automatically added to the event expression with these exceptions:
- Identifiers which only appear in wait or event expressions.
- Identifiers which only appear as a hierarchical_reg_identifier in the
reg_lvalue of the left hand side of assignments.
Nets and regs which appear on the right hand side of assignments, in
function and task calls, or case and conditional expressions shall all be
included by these rules.
CHANGE TO:
The event_expression list of an event control is a common source of bugs in
RTL simulations. Users tend to forget to add some of the nets or variables
read in the timing control statement. This is often found when comparing
RTL and gate level versions of a design. The implicit event_expression,
@*, is a convenient shorthand that eliminates these problems by adding all
nets and variables which are read by the statement (which can be a
statement group) of a procedural_timing_control_statement to the
event_expression.
All net and variable identifiers which appear in the statement will be
automatically added to the event expression with these exceptions:
- Identifiers which only appear in wait or event expressions.
- Identifiers which only appear as a [Use final BNF
terminology]hierarchical_variable_identifier in the [Use final BNF
terminology]variable_lvalue of the left hand side of assignments.
Nets and variables which appear on the right hand side of assignments, in
function and task calls, or case and conditional expressions shall all be
included by these rules.
------------------
Section 9.8.3, 1st, 2nd and 3rd paragraph:
DRAFT 4:
Both sequential and parallel blocks can be named by adding : name_of_block
after the keywords begin or fork. The naming of blocks serves several
purposes:
- It allows local regs to be declared for the block.
- It allows the block to be referenced in statements such as the disable
statement (Section 11).
All regs shall be static-that is, a unique location exists for all regs and
leaving or entering blocks shall not affect the values stored in them.
The block names give a means of uniquely identifying all regs at any
simulation time.
CHANGE TO:
Both sequential and parallel blocks can be named by adding : name_of_block
after the keywords begin or fork. The naming of blocks serves several
purposes:
- It allows local variables, parameters and named events to be declared for
the block.
- It allows the block to be referenced in statements such as the disable
statement (Section 11).
All variables shall be static-that is, a unique location exists for all
variables and leaving or entering blocks shall not affect the values stored
in them.
The block names give a means of uniquely identifying all variables at any
simulation time.
------------------
Section 10.2, 1st paragraph, 1st sentence:
DRAFT 4:
A task shall be enabled from a statement that defines the argument values
to be passed to the task and the regs that receive the results...
CHANGE TO:
A task shall be enabled from a statement that defines the argument values
to be passed to the task and the variables that receive the results...
------------------
Section 10.2.2, 3rd paragraph, 1st, 3rd and 5th bullets:
DRAFT 4:
- reg, integer, real, realtime, and time regs
- Memory references
- Concatenations of reg, integer, real, realtime and time regs
- Concatenations of memory references
- Bit-selects and part-selects of reg, integer, and time regs
CHANGE TO:
- reg, integer, real, realtime, and time variables
- Memory references
- Concatenations of reg, integer, real, realtime and time variables
- Concatenations of memory references
- Bit-selects and part-selects of reg, integer, and time variables
------------------
Section 10.2.2, 4th paragraph:
DRAFT 4:
The execution of the task enabling statement shall pass input values from
the regs listed in the enabling statement to the arguments specified within
the task. Execution of the return from the task shall pass values from the
task output and inout type arguments to the corresponding regs in the task
enabling statement. All arguments to the task shall be passed by value
rather than by reference (that is, a pointer to the value).
CHANGE TO:
The execution of the task enabling statement shall pass input values from
the expressions listed in the enabling statement to the arguments specified
within the task. Execution of the return from the task shall pass values
from the task output and inout type arguments to the corresponding
variables in the task enabling statement. All arguments to the task shall
be passed by value rather than by reference (that is, a pointer to the value).
------------------
Section 10.2.3, 1st paragraph:
DRAFT 4:
**** CHANGED BY STEVEN SHARP ****
------------------
Section 10.3.1 , 1st paragraph after Syntax 10-3 box, 3rd, 4th and fifth
sentences
DRAFT 4:
...A function specified without a range or type defaults to a one bit
register for the return value. If used, range_or_type shall specify the the
return value of the function is a real, and integer, a time a realtime or a
value with a range of [n:m] bits. A function shall have at least one input
declared. A function shall have at least one input declared.
CHANGE TO:
...A function specified without a range or type defaults to a one bit reg
for the return value. If used, range_or_type shall specify the return value
of the function is a real, integer, time, realtime or a value with a range
of [n:m] bits. A function shall have at least one input declared.
------------------
Section 10.3.2, 1st and 2nd paragraphs:
DRAFT 4:
The function definition shall implicitly declare a reg, internal to the
function, with the same name as the function. This reg either defaults to a
1-bit reg or is the same type as the type specified in the function
declaration. The function definition initializes the return value from the
function by assigning the function result to the internal reg with the same
name as the function.
It is illegal to declare another object with the same name as the function
in the scope where the function is declared. Inside a function, there is
an implied reg with the name of the function, which may be used in
expressions within the function...
CHANGE TO:
The function definition shall implicitly declare a variable, internal to
the function, with the same name as the function. This variable either
defaults to a 1-bit reg or is the same type as the type specified in the
function declaration. The function definition initializes the return value
from the function by assigning the function result to the internal variable
with the same name as the function.
It is illegal to declare another object with the same name as the function
in the scope where the function is declared. Inside a function, there is
an implied variable with the name of the function, which may be used in
expressions within the function...
------------------
Section 10.3.4, paragraph e):
DRAFT 4:
A function definition shall include an assignment of the function result
value to the internal reg that has the same name as the function name.
CHANGE TO:
A function definition shall include an assignment of the function result
value to the internal variable that has the same name as the function name.
------------------
Section 10.3.4, 2nd paragraph:
DRAFT 4:
This example defines a function called factorial that returns a 32-bit reg
value. The factorial function is called iteratively and the results are
printed.
CHANGE TO:
This example defines a function called factorial that returns an integer
value. The factorial function is called iteratively and the results are
printed.
------------------
Section 12.1.2, 4th paragraph, 1st sentence:
DRAFT 4:
A connection can be a simple reference to a reg or a net identifier, an
expression, or a blank...
CHANGE TO:
A connection can be a simple reference to a variable or a net identifier,
an expression, or a blank...
------------------
Section 12.3, 1st paragraph, last sentence:
DRAFT 4:
...These port names can differ from the names of the internal nets and regs
specified in the definition of module B.
CHANGE TO:
...These port names can differ from the names of the internal nets and
variables specified in the definition of module B.
------------------
Section 12.3.3, 2nd and 3rd paragraphs:
DRAFT 4:
If a port declaration includes a net_type or reg_type, then the port is
considered completely defined and it is an error for the port to be defined
again as a register or net. Because of this, all other aspects of the port
shall be defined in such a port declaration, including the signed and range
attributes if needed.
If a port declaration does not include a net_type or reg_type, then the
port can be again declared in a net or reg declaration. If the net or reg
is declared as a vector, the range specification between the two
declarations of a port declaration shall be identical. Once a name is
defined in a port declaration it shall not be defined again with the same
type or another type.
CHANGE TO:
If a port declaration includes a net type or variable type, then the port
is considered completely defined and it is an error for the port to be
defined again as a variable or net. Because of this, all other aspects of
the port shall be defined in such a port declaration, including the signed
and range attributes if needed.
If a port declaration does not include a net type or variable type, then
the port can be again declared in a net or variable declaration. If the net
or variable is declared as a vector, the range specification between the
two declarations of a port declaration shall be identical. Once a name is
defined in a port declaration it shall not be defined again with the same
type or another type.
------------------
Section 12.3.4, 2nd paragraph, 2nd sentence:
DRAFT 4:
...The ports direction, width, net or reg type, and whether the port is
signed or unsigned is completely described....
CHANGE TO:
...The ports direction, width, net or variable type, and whether the port
is signed or unsigned is completely described....
------------------
Section 12.3.9.2, 3rd paragraph, 1st bullet:
DRAFT 4:
- Regs
CHANGE TO:
- Variables
------------------
Section 12.3.9.2, 3rd paragraph, 3rd through 7th bullets:
DRAFT 4:
CHANGE TO:
Indent the 3rd through 7th bullets so that they are children of the second
bullet.
------------------
Section 12.5, 1st paragraph, 3rd sentence:
DRAFT 4:
...Variables V can be referenced if the name of the higher-level module or
its instance name is known...
CHANGE TO:
...Variables can be referenced if the name of the higher-level module or
its instance name is known...
------------------
Section 14.2.1, 1st paragraph, 2nd bullet:
DRAFT 4:
- The module path destination shall be a net or reg that is connected to a
module output port or inout port.
CHANGE TO:
- The module path destination shall be a net or variable that is connected
to a module output port or inout port.
------------------
Section 14.2.4.1, 1st paragraph, 2nd bullet:
DRAFT 4:
- Locally defined regs or nets or their bit-selects or part-selects
CHANGE TO:
- Locally defined variables or nets or their bit-selects or part-selects
------------------
Section 17.2, 1st paragraph, 3rd and 4th bullets:
DRAFT 4:
- Tasks that output values into regs
- Tasks and functions that read values from files and load into regs or
memories
CHANGE TO:
- Tasks that output values into variables
- Tasks and functions that read values from files and load into variables
or memories
------------------
Section 17.10.2, 4th paragraph, last sentence:
DRAFT 4:
If characters exist in the string available for conversion, which are
illegal for the specified conversion, the register shall be written with
the value 'bx.
CHANGE TO:
If characters exist in the string available for conversion, which are
illegal for the specified conversion, the variable shall be written with
the value 'bx.
------------------
<p>//********************************************************************//
// Cliff Cummings E-mail: cliffc@sunburst-design.com //
// Sunburst Design, Inc. Phone: 503-579-6362 / FAX: 503-579-7631 //
// 15870 SW Breccia Dr., Beaverton, OR 97007 //
// //
// Verilog & Synthesis Training //
// Verilog, VHDL, Synopsys, LMG, FPGA, Consulting and Contracting //
//********************************************************************//
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