From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Thu Feb 10 2000 - 09:04:36 PST
Here is another proposed change that needs a minor tweak to also include
the correct usage of "regs" and "variables"
Stu
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SOURCE: Cliff Cummings
09 Feb 2000
Draft 4, 12.3.9.2, bullet list at top of page 188
WAS:
The following external items shall not be connected to the output or inout
ports of modules:
-Regs
- Expressions other than
- A scalar net
- A vector net
- A constant bit-select of a vector net
- A part-select of a vector net
- A concatenation of the expressions listed above
PROPOSED IS:
The following external items shall not be connected to the output or inout
ports of modules:
-Regs
- Expressions other than
- A scalar net
- A vector net
- A constant bit-select of a vector net
- A part-select of a vector net
- A concatenation of the expressions listed above
CORRECTED PROPOSED IS:
The following external items shall not be connected to the output or inout
ports of modules:
- Variables (reg, integer, time, real and realtime)
- Expressions other than
- A scalar net
- A vector net
- A constant bit-select of a vector net
- A part-select of a vector net
- A concatenation of the expressions listed above
PROPOSED CHANGE:
More indentation on sub-list; explicitly list the data types that cannot
be used.
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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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