Re: Verilog 2000 attributes

From: Adam Krolnik (krolnik@lsil.com)
Date: Thu Feb 10 2000 - 16:11:39 PST

Good afternoon:

Thanks for the quick response. All the expression attributes seem to
be within elements of an expression (unary, binary, tertiary) and
primaries can not have an attribute (except for functions -
plain or system.)

Aside from removing attributes from the calls is there no other
way than using James' parenthesis trick

mod m1 ( (* on port *) ($stime), ( (* on func *) {$random)
       );

BTW, XL doesn't work with this, VCS only likes $random (and you get
one value.)

<p>I would be willing to sacrifice attributes on function calls I guess.

   Adam Krolnik
   Verification Mgr.
   LSI Logic Corp.
   Plano TX. 75074

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