Re: Verilog 2000 attributes

From: Michael McNamara (mac@verisity.com)
Date: Thu Feb 10 2000 - 17:38:37 PST


Steven Sharp writes:
> Are there any new ambiguities caused by moving attributes to the
> front of any constructs other than statements? I am particularly
> concerned with expressions.
>
> For example, if we still allow attributes on system functions, we
> now have an ambiguity even for functions that have parameters. It
> is the same one that James pointed out between an attribute on a
> system function and on a port expression that starts with a system
> function.
>
> Can you attach attributes to unary operators? If so, then you have
> the same problem again with distinguishing an attribute on a unary
> operator and on a port, if the port expression starts with a unary
> operator.

<p>Can I ask that someone load up the BNF for these attributes into a
yacc grammar, and see if this is going to work?

It seems we are sloshing these around like a bunch of drunk house
painters; and I don't think the result is going to be pretty.

Sounding like a broken record, I must comment that

(* x_coordinate=1027, y_coordinate=523 *)
acore c1 (
          (* rtl_clk *) .clk(clk),
          ...);

will typically be very unuseful, assuming the parent of c1 is
instantiated more than once...

-mac



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