Re: Verilog 2000 attributes

From: Steven Sharp (sharp@cadence.com)
Date: Thu Feb 10 2000 - 18:21:26 PST


> Can I ask that someone load up the BNF for these attributes into a
> yacc grammar, and see if this is going to work?

James did this to find the original problems, but I don't know that he
will have time for more testing.

<p>> It seems we are sloshing these around like a bunch of drunk house
> painters; and I don't think the result is going to be pretty.

It is scary to make such major changes at this point, with so little time
to analyze their validity. I do think that a consistent placement would
be better in the long run, if it is valid.

> Sounding like a broken record, I must comment that
>
> (* x_coordinate=1027, y_coordinate=523 *)
> acore c1 (
> (* rtl_clk *) .clk(clk),
> ...);
>
> will typically be very unuseful, assuming the parent of c1 is
> instantiated more than once...

To attach it to c1, it should really be placed before c1. Don't forget
that there could be a c2 declared on the same line.

That aside, this can be made useful even if the parent of c1 is instantiated
more than once and you need different attribute values. Just use parameterized
expressions and pass different values into different parents.

module parent(...);
parameter base_x = 0;
parameter base_y = 0;
...
acore (* x_coordinate=base_x+1027, y_coordinate=base_y+253 *)
        c1 (
           (* rtl_clk *) .clk(clk),
           ...);
endmodule

module top;

parent #(0,0) p1(...),
       #(0,2000) p2(...);
       

This is another reason why the values assigned to attributes needed to be
changed from an arbitrary string of characters to be constant_expression.
This already works with OVI attributes.



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