From: Steven Sharp (sharp@cadence.com)
Date: Fri Feb 11 2000 - 15:34:20 PST
Draft 4 page 15, section 2.8 , paragraph 3
WAS:
Each attribute_instance may appear in the Verilog description as a
module_item, a statement, or as a modifier to a particular statement.
See the syntax at the end of this section for a list of statements that
may have attributes attached to them.
PROPOSED IS:
An attribute_instance may appear in the Verilog description as a prefix
attached to a declaration, a module item, a statement, or a port connection.
It may appear as a suffix to a function call or an operator in an expression.
<p><p>Draft 4 page 16, section 2.8, entire page
WAS:
case (foo) (* attribute_a, attribute_b *)
<rest_of_case_statement>
or
case (foo) (* attribute_a=1, attribute_b=1 *)
<rest_of_case_statement>
or
case (foo) (* attribute_a // no value assigned
, attribute_b=1 *)
<rest_of_case_statement>
To attach the attribute_a attribute, but NOT the attribute_b attribute:
case (foo) (* attribute_a *) // attribute_b not specified
<rest_of_case_statement>
or
case (foo) (* attribute_a=1, attribute_b = 0 *)
<rest_of_case_statement>
To attach an attribute to a module definition:
module mod1 (* attribute_c *) (<port_list>);
or
module mod1 (* attribute_c=1 *) (<port_list>);
NOTE--Since the above example sets the attribute_c attribute in a module
definition, any instantiation of the module shall have that attribute,
unless explicitly overriden by a different value of that attribute on a
particular module instantiation:
mod1 (* attribute_c=0) synth1 (<port_list>);
To attach an attribute to a reg declaration:
reg [7:0] (* attr_d *) state1;
reg [3:0] (attr_d=1 *) state2, state3;
reg [3:0] reg1; // this reg does NOT have attr_d set
reg [3:0] (* attr_d=0 *) reg2; // nor does this one
To attach an attribute to an operator:
always @(posedge clk)
a = b + (* attr_e = "string" *) c;
This sets the value for the attribute attr_e to be the string string.
PROPOSED IS:
(* attribute_a, attribute_b *)
case (foo)
<rest_of_case_statement>
or
(* attribute_a=1, attribute_b=1 *)
case (foo)
<rest_of_case_statement>
or
(* attribute_a, // no value assigned
attribute_b=1 *)
case (foo)
<rest_of_case_statement>
To attach the attribute_a attribute, but NOT the attribute_b attribute:
(* attribute_a *) // attribute_b not specified
case (foo)
<rest_of_case_statement>
or
(* attribute_a=1, attribute_b = 0 *)
case (foo)
<rest_of_case_statement>
To attach an attribute to a module definition:
(* attribute_c *)
module mod1 (<port_list>);
or
(* attribute_c=1 *)
module mod1 (* attribute_c=1 *) (<port_list>);
NOTE--Since the above example sets the attribute_c attribute in a module
definition, any instantiation of the module shall have that attribute,
unless explicitly overriden by a different value of that attribute on a
particular module instantiation:
(* attribute_c=0 *)
mod1 synth1 (<port_list>);
To attach an attribute to a reg declaration:
(* attr_d *) reg [7:0] state1;
(* attr_d=1 *) reg [3:0] state2, state3;
reg [3:0] reg1; // this reg does NOT have attr_d set
(* attr_d=0 *) reg [3:0] reg2; // nor does this one
To attach an attribute to an operator:
always @(posedge clk)
a = b + (* attr_e = "string" *) c;
This sets the value for the attribute attr_e to be the string string.
To attach an attribute to a conditional operator:
a = b ? (* attr_f *) c : d;
<p><p>PROPOSED CHANGE:
Allow attributes on everything that Adam has requested, while removing
ambiguities. Make attribute position simple and consistent across most
objects. The suffix position for function calls and operators is necessary
to avoid ambiguity when a port connection expression begins with a function
call or unary operator. Make the examples compatible with this change.
The BNF also needs to be modified to match. I believe that the only places
that attributes will be needed will be at the start of these:
module_declaration
module_item
block_item_declaration
ordered_port_connection
named_port_connection
port_definition
statement
statement_or_null
function_statement
function_statement_or_null
at the end of these:
function_call
system_function_call
or equivalent places in primary,
and at the appropriate places (which already exist) in
expression
to cover unary_operator, binary_operator and conditional operators.
I think these are sufficient to get them everywhere desired through various
productions. However, if I appear to have missed any or put them on
anything inappropriate, let me know.
Here is the most recent list Adam sent out, which I think I have covered,
directly or indirectly:
module declarations
module or generate item
inout declaration
input declaration
output declaration
integer declaration
net declaration
reg declaration
time declaration
real declaration
realtime declaration
event declaration
function declaration
task declaration
block reg declaration
parameter declaration
local parameter declaration
specparam declaration
gate instantiation
module instantiation
ordered port connection
named port connection
udp declaration
udp output declaration
udp input declaration
initial construct
always construct
par(allel) block
seq(ential) block
statement
conditional statement
if else if statement
case statement
case_item
loop_statement
function statement
function case statement
function loop statement
function seq(ential) block
function conditional statement
function call
constant function call
system function call
unary operator
binary operator
conditional operator
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