From: Steven Sharp (sharp@cadence.com)
Date: Fri Feb 11 2000 - 23:04:35 PST
After a bit more consideration, I see a possible problem with not allowing
a statement attribute to appear after the delay_or_event_control. There
are a surprising (to me anyway) number of Verilog users who believe that in
a construct like
always @(posedge clk)
q = d;
the event control is an intrinsic part of the always, instead of realizing
that it is attached to the assignment statement. Grammatically they are
incorrect, but they will find it unnatural to put an attribute for the
assignment before the event control. I don't know if this is serious enough
to want to allow attributes to appear after the event control.
I really dislike putting attributes in the middle of function calls, and it
doesn't work for system functions without arguments. Another alternative
would be to switch port connections to use a suffix, and function calls and
operators to use a prefix. That choice was rather arbitrary anyway. It
would fix this particular problem, but would feel rather like "drunkenly
(or at least tiredly) sloshing the attributes around like buckets of paint"
in an attempt to fix the problem, to repeat a recent analogy. I am fairly
sure that it fixes it, but not as sure as my original version that assumed
statement attributes would appear before any delay or event controls.
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