From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Sat Feb 12 2000 - 09:26:35 PST
At 11:04 PM 2/11/00, Steven Sharp wrote:
>After a bit more consideration, I see a possible problem with not allowing
>a statement attribute to appear after the delay_or_event_control. There
>are a surprising (to me anyway) number of Verilog users who believe that in
>a construct like
>
> always @(posedge clk)
> q = d;
>
>the event control is an intrinsic part of the always, instead of realizing
>that it is attached to the assignment statement. Grammatically they are
The new @*, while technically controlling the execution of the next
statement, is even more part of the procedure, since it implies sensitivity
to all values used by the procedure.
<p>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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