Re: BTF Attribute proposal (problem from AMS Verilog)

From: Steven Sharp (sharp@cadence.com)
Date: Sat Feb 12 2000 - 14:05:35 PST


> I think attribute proposal in general is very good idea. One
> additional feature that is needed in AMS simulation is need for some
> kind of "compiler directive" (maybe not right solution) to assign
> default attribute to say every wire declaration. This is needed to
> tell analog equation solver say that all wires default to 3 volt attribute
> unless there is explicit attribute attached to wire.
> If there a way to do this in current proposal?

There is nothing built in to the attribute mechanism to set default values
or inherit values from elsewhere. This is beyond the scope of the current
proposal, which leaves semantics entirely up to the tool using them.

There is nothing preventing the tool from implementing such semantics
itself. An attribute attached to a module or module instance could be
interpreted by the tool as providing a default value for every object in
the scope under it.

BTW, if your example 3 volt attribute changes the semantics of the AMS
description, then I think that an attribute is a poor choice for specifying
that information. Attributes provide a catch-all mechanism for attaching
side information to the design. Properties that affect the meaning of
the AMS description should be specified in the main language itself.



This archive was generated by hypermail 2.1.4 : Mon Jul 08 2002 - 12:54:12 PDT and
sponsored by Boyd Technology, Inc.