From: Steven Sharp (sharp@cadence.com)
Date: Fri Feb 18 2000 - 13:35:33 PST
Draft 4 page 15, section 2.8 , paragraph 3
WAS:
Each attribute_instance may appear in the Verilog description as a
module_item, a statement, or as a modifier to a particular statement.
See the syntax at the end of this section for a list of statements that
may have attributes attached to them.
PROPOSED IS:
An attribute_instance may appear in the Verilog description as a prefix
attached to a declaration, a module item, a statement, or a port connection.
It may appear as a suffix to an operator or a Verilog function name in an
expression.
<p>Draft 4 page 15, section 2.8, first example
WAS:
<verilog_text>
...
<yet_more_verilog_text>
PROPOSED CHANGE:
Delete this example. It implies things about how attributes can be used
that may be misleading. They cannot be used at arbitrary places in Verilog
text, but must be attached to specific items. We don't yet have a good
solution to the translate_on/translate_off usage.
<p>Draft 4 page 16, section 2.8, entire page
WAS:
case (foo) (* attribute_a, attribute_b *)
<rest_of_case_statement>
or
case (foo) (* attribute_a=1, attribute_b=1 *)
<rest_of_case_statement>
or
case (foo) (* attribute_a // no value assigned
, attribute_b=1 *)
<rest_of_case_statement>
To attach the attribute_a attribute, but NOT the attribute_b attribute:
case (foo) (* attribute_a *) // attribute_b not specified
<rest_of_case_statement>
or
case (foo) (* attribute_a=1, attribute_b = 0 *)
<rest_of_case_statement>
To attach an attribute to a module definition:
module mod1 (* attribute_c *) (<port_list>);
or
module mod1 (* attribute_c=1 *) (<port_list>);
NOTE--Since the above example sets the attribute_c attribute in a module
definition, any instantiation of the module shall have that attribute,
unless explicitly overriden by a different value of that attribute on a
particular module instantiation:
mod1 (* attribute_c=0) synth1 (<port_list>);
To attach an attribute to a reg declaration:
reg [7:0] (* attr_d *) state1;
reg [3:0] (attr_d=1 *) state2, state3;
reg [3:0] reg1; // this reg does NOT have attr_d set
reg [3:0] (* attr_d=0 *) reg2; // nor does this one
To attach an attribute to an operator:
always @(posedge clk)
a = b + (* attr_e = "string" *) c;
This sets the value for the attribute attr_e to be the string string.
PROPOSED IS:
(* full_case, parallel_case *)
case (foo)
<rest_of_case_statement>
or
(* full_case=1, parallel_case=1 *)
case (foo)
<rest_of_case_statement>
or
(* full_case, // no value assigned
parallel_case=1 *)
case (foo)
<rest_of_case_statement>
To attach the full_case attribute, but NOT the parallel_case attribute:
(* full_case *) // parallel_case not specified
case (foo)
<rest_of_case_statement>
or
(* full_case=1, parallel_case = 0 *)
case (foo)
<rest_of_case_statement>
To attach an attribute to a module definition:
(* optimize_power *)
module mod1 (<port_list>);
or
(* optimize_power=1 *)
module mod1 (<port_list>);
To attach an attribute to a module instantiation:
(* optimize_power=0 *)
mod1 synth1 (<port_list>);
To attach an attribute to a reg declaration:
(* fsm_state *) reg [7:0] state1;
(* fsm_state=1 *) reg [3:0] state2, state3;
reg [3:0] reg1; // this reg does NOT have fsm_state set
(* fsm_state=0 *) reg [3:0] reg2; // nor does this one
To attach an attribute to an operator:
a = b + (* mode = "cla" *) c;
This sets the value for the attribute mode to be the string cla.
To attach an attribute to a Verilog function call:
a = add (* mode = "cla" *) (b, c);
To attach an attribute to a conditional operator:
a = b ? (* no_glitch *) c : d;
<p><p>PROPOSED CHANGE:
Allow attributes on everything that Adam has requested (except system function
calls), while removing ambiguities. Make attribute position simple and
consistent across most objects. The suffix position for function calls and
operators is necessary to avoid ambiguity when a port connection expression
begins with a function call or unary operator. Make the examples compatible
with this change. Use meaningful attributes in examples, as requested by
James.
The BNF also needs to be modified to match. I believe that the only places
that attributes will be needed will be at the start of these:
module_declaration
udp_declaration
module_item
module_or_generate_item
block_item_declaration
task_item_declaration
ordered_port_connection
named_port_connection
port_definition
task_port_item
function_port_list
udp_input_declaration
udp_output_declaration
udp_reg_declaration
statement
statement_or_null
function_statement
function_statement_or_null
at the appropriate place in
function_call
and at the appropriate places (which already exist) in
expression
to cover unary_operator, binary_operator and conditional operators.
I think these are sufficient to get them everywhere desired through various
productions. However, if I appear to have missed any or put them on
anything inappropriate, let me know. This list already includes the ones
caught by James. Note that it may be cleaner to put them on lower level
productions like input_declaration, instead of on the higher level
productions that eventually reach those. This is up to Cliff.
Here is the most recent list Adam sent out, which I think I have covered,
directly or indirectly (except system_function_call):
module declarations
module or generate item
inout declaration
input declaration
output declaration
integer declaration
net declaration
reg declaration
time declaration
real declaration
realtime declaration
event declaration
function declaration
task declaration
block reg declaration
parameter declaration
local parameter declaration
specparam declaration
gate instantiation
module instantiation
ordered port connection
named port connection
udp declaration
udp output declaration
udp input declaration
initial construct
always construct
par(allel) block
seq(ential) block
statement
conditional statement
if else if statement
case statement
case_item
loop_statement
function statement
function case statement
function loop statement
function seq(ential) block
function conditional statement
function call
constant function call
system function call
unary operator
binary operator
conditional operator
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