From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Tue Jun 27 2000 - 07:37:46 PDT
Cadence - Steve Sharp
Synopsys - Karen Pieper
ModelTech - Randy Misustin
I believe there is an errata in the ballot Verilog Standard that has
existed since before the 1995 IEEE Standard and I would like to get it
fixed. I am about to send in the following proposal to correct the errata
but wanted to make sure that the big-three agree concerning the algorithm.
The following was in response to an e-mail that I received about blocking
and nonblocking assignments.
A quick response, particularly from the big-3, would be appreciated.
Regards - Cliff
Shalom Bresticker, a valued member of my Behavioral Task Force on the
Verilog Standards Group also raised this issue a couple of times in the
past five years. I am embarrassed to say that we forgot to correct the
section 9 inconsistencies that you have pointed out. This even slipped into
the Verilog-2000 LRM.
I need to contact the major Verilog vendors to verify that this is indeed
an error in the Verilog Standard documentation. If all vendors agree, I
will propose the following errata change to the Verilog-2000 standard:
Std P1364/D5 (5/3/00), section 9.2.2, pg. 128, Starting with the first
paragraph under Example 3 and continuing to the end of the page (note,
example 5 and accompanying text are the same as on page 128) - (Mike
MacNamara looked this over and agreed with the substance and wording of the
errata fix)
PROPOSED NEW WORDING
When multiple nonblocking assignments are scheduled to occur to the same
variable in a particular time slot from different procedural blocks, the
order in which the assignments are evaluated is not guaranteed - the final
value of the variable is indeterminate. When multiple nonblocking
assignments are scheduled to occur to the same variable in a particular
time slot from the same procedural block, the order in which the
assignments shall be performed is the order the statements were executed
and the final value of the variable shall be the last value scheduled, as
previously described in section 5.4.1. As shown in the following example,
the value of reg a at the end of time step 4 is 1.
Example 4:
module multiple2 (out);
output out;
reg a;
initial a = 1;
// The assigned value of reg a is determinate
initial begin
a <= #4 0; // schedules a = 0 at time 4
a <= #4 1; // schedules a = 1 at time 4
end // At time 4, a = 1
endmodule
If the simulator executes two procedural blocks concurrently, and if these
procedural blocks contain nonblocking assignment operators to the same
variable, the final value of that variable is indeterminate. For example,
the value of reg a is indeterminate in the following example.
Example 5:
module multiple3 ;
reg a;
initial a = 1;
initial a <= #4 0; // schedules 0 at time 4
initial a <= #4 1; // schedules 1 at time 4
// At time 4, a = ??
// The assigned value of the reg is indeterminate
endmodule
END OF PROPOSAL
Thanks for reminding me that this inconsistency still exists in the Verilog
LRM.
- Cliff
From: "Vigyan Singhal" <vigyan@home.com>
>Cliff,
>
>I have a comment/question on your following myth:
>
>>( ESNUG 347 Item 1 ) ---------------------------------------------
>[3/23/00]
>>
>>From: Cliff Cummings <cliffc@sunburst-design.com>
>>Subject: Cliff's SNUG'00 1st Place Paper On Nonblocking Verilog Assignments
>>
>> [...]
>>
>>15.3 Multiple Nonblocking Assignments To The Same Variable
>>
>> Myth: "Making multiple nonblocking assignments to the same variable
>> in the same always block is undefined"
>>
>> Truth: Making multiple nonblocking assignments to the same variable
>> in the same "always" block is defined by the Verilog Standard.
>> The last nonblocking assignment to the same variable wins!
>>
>>Quoting from the IEEE 1364-1995 Verilog Standard [2], pg. 47, section 5.4.1
>>on Determinism:
>>
>> "Nonblocking assignments shall be performed in the order the
>> statements were executed. Consider the following example:
>>
>> initial begin
>> a <= 0;
>> a <= 1;
>> end
>>
>> When this block is executed, there will be two events added to the
>> nonblocking assign update queue. The previous rule requires that
>> they be entered on the queue in source order; this rule requires
>> that they be taken from the queue and performed in source order as
>> well. Hence, at the end of time-step 1, the variable a will be
>> assigned 0 and then 1."
>>
>>Translation: "The last nonblocking assignment wins!"
>
>The Verilog LRM appears to be inconsistent on this issue. I picked up
>the following from section 9.2 on "Procedural assignments":
>
>"When multiple non-blocking assignments are scheduled
>to occur in the same register in a particular time slot, the
>order in which the assignments are evaluated is not
>guaranteed--the final value of the register is indeterminate.
>As shown below, the value of register a is not known until
>the end of time step 4.
>
>module multiple2 (out);
>output out
>reg a;
>
>initial a = 1;
>// The register's assigned value is indeterminate
>initial begin
> a <= #4 0; // schedules a = 0 at time 4
> a <= #4 1; // schedules a = 1 at time 4
>end // At time 4, a = ??
>endmodule
>"
>
>This seems to contradict your earlier quote from Section 5.4.1.
>Which is correct, and why does the LRM seem to be inconsistent?
>In fact, I have seen an example (more complicated than this
>one) where DC picked the first assignment, but we thought
>it wasn't DC's fault since the RTL was not deterministic.
>Perhaps we should have treated it as a synthesis bug.
>
>-Vigyan Singhal
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