From: Adam Krolnik (krolnik@lsil.com)
Date: Wed Sep 06 2000 - 08:37:39 PDT
Good morning Shalom;
You wrote:
"We designed an ATM controller chip."
Cadence's proposal is to use a task inside a module and instantiate
the module multiple times - then use a case statement to select
the one you want, or call it directly.
They countered that since there is no spawning of a task call, having
reentrant tasks is of limited use.
<p>Could you comment a little more on what you did (multiple always blocks,
multiple events, etc.) to get it to work, and how you might reimplement
it if reentrant tasks would be available. You see, their first comment
is how the feel about it - 'no known application' "it's not useful
enough." An example would provide justification.
You also commented:
>The lack of "generate" is universally felt to be one of the biggest >missing features.
Cadence's big objection, IMHO, is that there needs to be more
specification
about how it is supposed to work. All the examples show cases that need
to be considered and may be implemented differently.
I will agree that 'generated identifiers are strings, not indexable
arrays'
is an unfortunate shortcoming, along with only generating module items -
not items within blocks, etc.
It does sound funny that (some of) the NO votes came from a block of
Cadence engineers. The objections are to 4 of the top 5 USER recommended
features to be added to Verilog.
<p> Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:54:13 PDT
and
sponsored by Boyd Technology, Inc.