From: Anders Nordstrom (andersn@nortelnetworks.com)
Date: Thu Oct 05 2000 - 06:10:19 PDT
Adam,
I tried to run the code through a couple of tools and they all
say it is a syntax error.
Verilog-XL, VCS, SYSTEMSIM, DesignCompiler and VeriLint
all report an error.
I don't see any particular value in allowing the syntax in line 5
since it will require many tools to change to be compatible with
the standard.
Regards,
Anders
<p>Adam Krolnik wrote:
> Good afternoon Cliff;
>
> I just found an interesting example of a combination of declarations
> that are not allowed by the current BNF.
>
> Doubt it is worth changing, but an interesting thing.
>
> %cat -n /tmp/a.v
> 1 module testwire;
> 2
> 3 wire a, b, c;
> 4 wire d = 0, e = 0, f = 0;
> 5 wire g, h = 0, i;
> 6
> 7 endmodule
>
> VCS and XL say line 4 has an error - no mixing of net declarations
> with net declaration assignments.
>
> Surelint says (reasonably) this is okay.
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
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