LRM Ballot comment proposals to review

From: Anders Nordstrom (andersn@nortelnetworks.com)
Date: Fri Oct 06 2000 - 07:55:17 PDT


Dear BTF members,

Please review my proposals to address Peter Flake's ballot comments
listed below. We will review and vote on them at the next BTF conference
call on October 12 or 13.

Regards,

        Anders

<p><p>Comments from Peter Flake:
--------------------------
Comment 1. page 143

event e [0:3];
always @ e [i] $display ("event happened");

What happens when i changes? Does the always block trigger?

PROPOSAL: The always block does not trigger, changing i is
 not equivalent to triggering an event. Add the following
 text to the sentence above Syntax 9-10 on page 143:
 "An event is not made to occur by changing the index
 of an event array."

---------------------------------------------------------------
Comment 2: pages 15 and 16

Attributes have semicolons in the grammar but not in the examples. Which
is correct?

PROPOSAL: There should not be semicolons after attributes. Remove the
 semicolon from the attribute_instance grammar in Syntax 2-3
 on page 15.

------------------------------------------------------------------------
Comment 3: page 188

Port declarations can include input declarations, which have semicolons in
the grammar but not in the example on page 191. Which is correct?

PROPOSAL: There should be no semicolon in the declarations so the grammar
 is incorrect. The semicolon after the input, output or inout
 declaration is required in the old style of declarations but not
 in the new ANSI like one.
 Remove the semicolon at the end of inout_declaration,
 input_declaration and output_declaration in Syntax 12-6 on page 189
 and in Annex A2.1.2 on page 776. Add a semicolon after
 port_declaration under module_item ::= in A1.5 on page 774.

--------------------------------------------------------------------------
Comment 4: page 78

I believe that variable initializations should occur before initial blocks,
rather than being unordered with respect to initial blocks.

PROPOSAL: No change. This is equivalent to assigning the same variable
 in two different initial blocks.

------------------------------------------------------------------
Comment 5: page 124

Bit select of an integer or time variable is not explained, e.g. what the
bit numbers are. It seems strange that it is not treated like a scalared
reg, which cannot be accessed by bit.

PROPOSAL: No change. On page 34 it says that integers behave like signed
 reg and time behaves like unsigned reg.

--------------------------------------------------------------------
Comment 6: page 41

Attributes are not mentioned in the discussion of name spaces

PROPOSAL: Add attributes to module name space. Add attributes to
 the list in the second paragraph from the bottom on
 page 41.

-------------------------------------------------------------------

Attachment Converted: "C:\Documents and Settings\stefen\Application Data\Qualcomm\Eudora\andersn37.vcf"



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