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Date: Fri, 27 Oct 2000 08:51:14 -0500
From: Adam Krolnik <krolnik@lsil.com>
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To: Steven Sharp <sharp@cadence.com>,
<@dt203.lsil.com@dt203.lsil.com@dt203.lsil.com@dt203.lsil.com@dt203.lsil.com@dt203.lsil.com@dt203.lsil.com@dt203.lsil.com@dt203.lsil.com>
CC: btf@boyd.com@dt203.lsil.com
Subject: Re: JohnW Comment 66 - 70 Ballot LRM Feedback
References: <200010270008.UAA02198@quicksand.Cadence.COM>
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<p>Good morning all;
Steven wrote:
>I agree that `resetall should not reset `line, as suggested here. The
>defaults are stated or implied elsewhere in the section, but may not be
>clear to everyone. The default for `timescale does not appear to be
>stated. Verilog-XL uses 1s/1s, which is generic but not useful for real
>hardware. NC-Verilog uses 1ns/1ns. Other defaults appear to be
>`endcelldefine, `default_nettype wire, and `nounconnected_drive.
The text for `line does specify that resetall has no effect on it.
Addition of text in the `resetall directive would be reflective,
and not a new feature.
There is no 'default' value for timescale that all simulators will
agree upon. How about we flip a coin or draw straws for a default?
Choices include
A. 1ns/1ns
B. 1s/1s
C. 10ns/10ns
D. 100ps/100ps
How about we vote on a number - the value associated with the number
will not be shown until all votes are in - that way noone can
be held accountable for voting for the 'wrong' default...
I'll pick #3...
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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