From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Fri Oct 27 2000 - 09:07:05 PDT
At 07:50 PM 10/12/00 -0700, you wrote:
>Here's another good question for consideration at tomorrow's conference call.
>
>Stu
>
>>From: Dhiraj Raj <draj@cupertino.synopsys.com>
>>Date: Tue, 10 Oct 2000 10:58:25 -0700 (PDT)
>>To: stuart@sutherland-hdl.com
>>Subject: Re: Verilog 2000
>>
>>I have one more question. Pl. pass it on to the appropriate task force if
>>you don't have a definite answer. The grammar seems to allow "empty" named
>>parameter assignments like...
>>
>>module mux;
>>parameter WIDTH = 8;
>>endmodule
>>
>>module chip;
>>mux #(.WIDTH()) mux1();
>>endmodule
>>
>>Is this acceptable? What is the value of WIDTH for mux1?
>>
>>- Dhiraj
Concerning questions related to the grammar (BNF), it would be helpful to
include with the question, appropriate references to the BNF sections that
helped form the question. I spent some time searching through the BNF to
try to find the rational behind Dhiraj's question, but could not see where
the BNF permitted empty named parameter assignments.
Since, in theory, we are currently supposed to be finishing up our work by
answering ballot-related questions, post-ballot questions without
sufficient supporting references only slow down our effort to finish.
Although in theory, we should not even consider non-ballot questions, the
BTF is looking to release an exceptionally professional document and we are
in fact considering some non-ballot questions. Dhiraj's observation, if
true, is one that we would want to address.
Friendly side note: if this question is related contract work that you did
for the Synopsys VCS team, you probably should join the BTF conference
calls and answer Dhiraj's questions personally as opposed to re-directing
them to the BTF to address. In theory, Dhiraj should be working directly
through Karen Peiper of Synopsys, who is a member of the BTF to resolve
Synopsys' concerns with the proposed Verilog Standard.
Regards - Cliff Cummings
Chair - Behavioral Task Force of the Verilog Standards Group
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