From: James A. Markevitch (jam@magic.com)
Date: Wed Nov 01 2000 - 21:48:19 PST
> This may not be of interest to the NC group, but the Verilog-2000 grammar
> for ANSI-style ports requires two tokens of lookahead:
>
> module m(input a, b);
> ^
> module m(input a, input b);
> ^
>
> Upon encountering the ',', a yacc parser cannot tell if the list of names
> associated with the 'input' keyword will continue, or if another keyword
> will occur.
This is certainly the case, although the grammar is unambiguous. This is
not the only place in the grammar which requires more than one token of
lookahead, but this seems to be one which may cause more indigestion to
implementors than the others.
There are some places in the grammar which require an infinite lookahead
to resolve. I am pretty sure that the tools on the market today ignore
this and just assume an "obvious" parsing, rather than a technically
correct one. This actually came up during one of the BTF telecon's and
I believe that one of vendor representatives confirmed this.
So, the new grammar breaks LALR(1) parsing for a common-case: "ANSI-style"
declarations. Even through the grammar was already broken for LALR(1),
the other cases were pretty obscure, so nobody probably noticed. We
should probably address this at the next conference call (VSG on Monday).
In the meantime, do we want to consider any alternatives? Switch back
to using semicolons for separation? Allow exactly one signal to be
declarated per "input", "output", or "inout" in ANSI declarations?
Other? Or just require implementors to be more clever than just using
a simple Yacc parser?
My personal preference is for the semicolon-separated list, as we had it
in draft 5 (we could make the trailing semicolon optional, though). This
was *not* the BTF's preferred syntax, though.
It would be interesting to hear what the vendors have to say on this matter.
As a tool-writer, I find this grammar annoying to implement, but it can be
worked-around using a few ugly kludges.
James Markevitch
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