Re: shift-reduce conflict in verilog-2000 grammar

From: Adam Krolnik (krolnik@lsil.com)
Date: Thu Nov 02 2000 - 06:05:46 PST


Good morning all;

Just for clarity, we had hoped for the ability to write code
this way...

module m {
 input a, b,
 output whatever,
 input more_inputs, and_still_more,
 inout thrown_in_for_completeness
 );

Having to one write like:

module m {
 input a,
 input b,
 output whatever,
 input more_inputs,
 input and_still_more,
 inout thrown_in_for_completeness
 );

Makes the port list textually longer...

Uuuuuh, here's my chance to propose optional commas! Or in this case
unnecessary commas :)

Can we do away with the comma separation between the port declarations?
I.e. instead of replacing semicolon at the end of a port declaration
with a comma, replace it with nothing. This way, one has fewer
tokens, and punctuation.

module m {
 input a, b // No comma
 output whatever // no comma
 input more_inputs, and_still_more // no comma
 inout thrown_in_for_completeness // no comma
 );

<p><p> Adam Krolnik
   Verification Mgr.
   LSI Logic Corp.
   Plano TX. 75074



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