From: Adam Krolnik (krolnik@lsil.com)
Date: Tue Dec 05 2000 - 06:39:55 PST
Good morning Paul;
> generate and configuration management (basicly in both cases you
> need to perform elaboration to decide which are the top modules,
> but you need to know which are then top modules in order to do
> elaboration, .... do you start with chickens? or eggs? I think
Depending on your usage model, you might have these problems or not.
If one includes configs in the verilog source text, you can look to
these
(specifically the one selected) for what the top level module(s) are.
If your usage model is to compile all verilog source into libraries,
then
in the end, one will ask to compile a specific configuration - and
mention
one specific config. This will then define what is the top modules, etc.
If one does not use any configuration blocks, then you are resolved to
searching for a top level module in the source not unconditionally
instantiated. You show a strange possibility of two modules, you may
then also need to consider this example...
module A(a, b, c);
input a, b;
output c;
parameter inside = 1;
generate
if (inside == 1)
A ohhhhnoooo (a, b, c);
endgenerate
endmodule
Also, the -L switch was intended for specification of library names
(ordered) to
be searched, to override lib.map or other files. It should not read a
filename.
Thanks for your questions.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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