From: Daryl Stewart (Daryl.Stewart@cl.cam.ac.uk)
Date: Wed Dec 13 2000 - 06:47:43 PST
Hi all,
I know this is very late in the day but I've noticed that no change has been
made to section 6.1.3 in the recently sent "1364.A.pdf" and I believe the
description does not make clear the behaviour caused by the combination of a
net delay and a driver delay.
The closest it comes is "When there is a continuous assignment in the
declaration, the delay is part of the continuous assignment and is not a net
delay. Thus it is not added to the delay of other drivers". Which seems to
imply that "When there is no continuous assignment in the declaration, the
delay is a net delay. Thus it is added to the delay of other drivers". Which
is not true.
In particular, step b) is confusing since it refers to "the value currently
scheduled to propagate to the left-hand side".
Consider:
module foo();
reg r1, r2;
wire #10 wireA; // specifies a net delay of 10 for wireA
wire wireB; // specifies a net delay of 0 for wireB
wire #5 wireC = r1; // specifies no net delay for wireC
// and a driver delay of 5 for this assign
assign #10 wireA = r1; // specifies a driver delay of 10 for this assign
assign wireA = r2; // specifies no driver delay
assign #5 wireB = r1; // specifies a driver delay of 5 for this assign
initial r1 = 0;
initial r2 = 0;
initial begin
#5 $display("%b %b %b %b %b",r1, r2, wireA, wireB, wireC, $time);
#0 $display("%b %b %b %b %b",r1, r2, wireA, wireB, wireC, $time,"+#0");
#95 r1 = 1;
#5 r1 = 0;
#95 r1 = 1;
#15 r1 = 0;
end // initial begin
initial begin
$display("r1 r2 A B C");
$monitor("%b %b %b %b %b",r1, r2, wireA, wireB, wireC, $time);
end // initial begin
endmodule // foo
/* verilog foo.cv
VERILOG-XL 2.5 Dec 13, 2000 14:22:03
Highest level modules:
foo
r1 r2 A B C
0 0 x x x 0
0 0 x x 0 5
0 0 x 0 0 5+#0
0 0 x 0 0 5
0 0 0 0 0 20
1 0 0 0 0 100
0 0 0 1 1 105
0 0 0 0 0 110
1 0 0 0 0 200
1 0 0 1 1 205
0 0 0 1 1 215
0 0 x 0 0 220
0 0 0 0 0 235
0 simulation events (use +profile or +listcounts option to count) + 3
accelerated events
CPU time: 0.4 secs to compile + 0.2 secs to link + 0.1 secs in simulation
End of VERILOG-XL 2.5 Dec 13, 2000 14:22:09
*/
Notice that
a) wireC changes one #0 before wireB, since it has no net delay section.
b) the assignment of 1 to r1 at time 200 makes it through the driver delay of
#10 associated with "assign #10 wireA = r1" and although r1 changes to 0 before
the 1 reaches wireA it is not descheduled as one might surmise from the
present description.
c) when the 1 from r1 at time 200 completes its driver delay section it is
combined with the 0 from "assign wireA = r2" to schedule a value of x at time
220.
I have attached a new description which I think is suitable for 6.1.3., based
on the observed behaviour of Verilog-XL 2.5.
I mentioned this once before but got no response. Could someone let me know if
this is just plain irrelevant... ;)
cheers
Daryl
<p><p><p><p>Attachment Converted: "C:\Documents and Settings\stefen\Application Data\Qualcomm\Eudora\Proposed.6.1.3.txt"
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