Error in IEEE 1364-2001

From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Mon Mar 12 2001 - 01:30:47 PST

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I just noticed that the following error was not fixed in sectino 12.3.3
(as of Draft 6, which is what I have).
To quote Steven Sharp:
 "Shalom is correct. To be consistent with everything else about
port
 connections, the input nets should be "tied together", not "ored".
 If the ports get collapsed (as most ports do), there is no way they
 could be "ored". The same applies if the ports were declared
as outputs
 or inouts.
If this goes in, it will be a new error, not a clarification."
Shalom
-------- Original Message --------
<table BORDER=0 CELLSPACING=0 CELLPADDING=0 >
<tr>
<th ALIGN=RIGHT VALIGN=BASELINE NOWRAP>Subject: </th>

<td>Re: Minutes from today's VSG call</td>
</tr>

<td>Shalom Bresticker <shalom@msil.sps.mot.com></td>
</tr>

<tr>
<th ALIGN=RIGHT VALIGN=BASELINE NOWRAP>Organization: </th>

<td>Motorola Semiconductor Israel, Ltd.</td>
</tr>

<td>Lynn Horobin <lynnh1@ix.netcom.com></td>
</tr>

<td>Daryl.Stewart@cl.cam.ac.uk, S1364@eda.ics.es.osaka-u.ac.jp, adamk@cyrix.com,
alec@fintronic.com, andersn@nortel.ca, anderson@acuson.com, bob@simucad.com,
carl.ruggiero@infocus.com, chas@cadence.com, clhuang@ne.mediaone.net, dinesh@synopsys.com,
dkf@synopsys.com, drew@surefirev.com, elkind@cadence.com, furui@n022.saskg.semicon.sony.co.jp,
gmoretti@veribest.com, john@simucad.com, kurt@wsfdb.com, mac@surefirev.com,
mannan@dsmtech.com, marek@cadence.com, mno1@ricochet.net, naveen@lsil.com,
pieper@synopsys.com, prabhu@lsil.com, roberts@cadence.com, sharp@cadence.com,
skp@cadence.com, stefen@boyd.com, stuart@sutherland-hdl.com, tfitz@cadence.com,
vhberman@worldnet.att.net, vivek@veri-log.com, wadswort@poci.amis.com</td>
</tr>

<tr>
<th ALIGN=RIGHT VALIGN=BASELINE NOWRAP>References: </th>

Lynn Horobin wrote:
<blockquote TYPE=CITE>IEEE 1364 Verilog Standards
Group
 Teleconference Minutes
 February 11, 2000
 
D) Port restrictions clarification - e-mail from
Anders Nordstrom - 2/10/00 (Subject: BTF - VSG Vote on Friday: Port declaration
errata)
 Motion: Define the behaviour in two previously
undocumented cases of port declarations. Draft 4 page 186 just above
section 12.3.7, Add the following text: Multiple module instance port connections
are not allowed i.e. the following example is illegal:
Example:
 module test;
 a ia (.i (a), .i (b),
// illegal connection of input port twice.
 .o (c), .o
(d), // illegal connection of output
port twice.
 .e (e), .e
(f)); // illegal connection of inout port
twice.
 endmodule
 Proposed: Cliff Cummings
 Seconded: Stefen Boyd
 Motion passed unanimously.
Add the following text after the last example. Draft
4 page 184 just above section 12.3.4
 module same_input (a,a);
//This is legal. The inputs are ored
 input a;
// together.
 Proposed: Cliff Cummings
 Seconded: Stefen Boyd
 Motion passed unanimously.</blockquote>
This is not logical.
It means that if one port is connected to 0 and the other port to 1,
the 1 takes precedence.
 That's the meaning of "or".
It should be a multiple continous assignment, as described in 5.6.6.
 If it is connected to 0 and 1, the result is X (assuming equal strength).
 If one is stronger than the other, the stronger one takes precedence.
<pre>--

************************************************************************
Shalom Bresticker email: shalom@msil.sps.mot.com
Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522444
<a href="http://www.motorola-semi.co.il/">http://www.motorola-semi.co.il/
</a>************************************************************************</pre>

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