From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Mon Mar 12 2001 - 01:43:47 PST
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The following question came up on comp.lang.verilog.
<p>I am not sure of the answer and did not find explicit mention in
1364.
<p>Is "module qq ( .v(a), .v(b) )" legal, and if so, what does
it do ?
<p>(External port name is v. Internal nets/variables a and b are connected
to it.)
<pre>--
**************************************************************************
Shalom Bresticker Shalom.Bresticker@motorola.com
Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522890
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