From: Michael McNamara (mac@verisity.com)
Date: Wed Mar 14 2001 - 05:25:17 PST
Precedence: bulk
<p>Yes, you are correct. My apologies.
Shalom Bresticker writes:
> [1 <text/plain; us-ascii (7bit)>]
> Michael,
>
> 5.6.6 in 1364-1995 describes a different situation.
>
> 5.6.6 describes one internal signal which is connected to two external ports.
> I asked about one external port which is connected to two internal signals.
>
> By the way, the example in 5.6.6 was moved to 12.3.3.
>
> Shalom
>
>
> Michael McNamara wrote:
>
> > Shalom Bresticker writes:
> > >
> > > The following question came up on comp.lang.verilog.
> > >
> > > I am not sure of the answer and did not find explicit mention in 1364.
> > >
> > > Is "module qq ( .v(a), .v(b) )" legal, and if so, what does it do ?
> > >
> > > (External port name is v. Internal nets/variables a and b are connected to it.)
> >
> >
> > The 'Section 5.6.6 Port Connections'
> >
> > has described this exact situation, since 1364-1995 came out.
> >
> > Actually, there the example is module foo(.a(p), .b(p));
> >
> > Yes, 5.6.6 is the wrong place, and there was some discussion of moving
> > this to section 12, but I have no access to the ballot version so I
> > don't know if this was done.
>
> --
> **************************************************************************
> Shalom Bresticker Shalom.Bresticker@motorola.com
> Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
> P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522890
> **************************************************************************
>
>
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>
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