From: Jayaram Bhasker (jbhasker@cadence.com)
Date: Fri Jun 22 2001 - 06:01:24 PDT
Precedence: bulk
Cliff, Paul:
On further reading, the following line in 12.1.3.1 says "A genvar is an
integer that is local to and shall .... or if the genvar is
set to a negative value, this shall be an error.".
So in Paul's example, an error would be reported when i gets a negative value.
- bhasker
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> Date: Thu, 21 Jun 2001 15:46:46 -0700
> To: pgraham
> From: "Clifford E. Cummings" <cliffc@sunburst-design.com>
> Subject: Fwd: Genvars only positive?
> Cc: btf@boyd.com
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>
> Hi, Paul -
>
> Comments interspersed below.
>
> Regards - Cliff
>
> >Date: Thu, 21 Jun 2001 13:55:43 -0700
> >To: btf@boyd.com
> >From: Stuart Sutherland <stuart@sutherland-hdl.com>
> >Subject: Fwd: Genvars only positive?
> >
> >Cliff,
> >
> >Does anyone in your group want to comment on this (please copy me)?
> >
> >Thanks,
> >Stu
> >
> >>Sender: pgraham@cadence.com
> >>Date: Wed, 20 Jun 2001 16:50:55 -0400
> >>From: Paul Graham <pgraham@cadence.com>
> >>Organization: Cadence Design Systems
> >>To: stuart@sutherland-hdl.com
> >>Subject: Genvars only positive?
> >>
> >>Stuart,
> >>
> >>I'm looking at Draft 4 of the LRM, section 12.1.3.1, where it says:
> >>
> >> A genvar is a positive integer that is local to and shall only be
> >>used
> >> within a generate loop that uses it as an index variable.
> >>
> >>Restricting a genvar to be positive actually violates some examples in
> >>the LRM.
>
> Could you be more specific? Which examples? I believe we determined that 0
> is part of the positive integer space, so at first glance, I did not find
> any of the examples that violated this rule.
>
> >>Restricting it to be non-negative means you can't do something like:
> >>
> >> genvar i;
> >> generate
> >> for (i = 7; i >= 0; i = i - 1) ...
> >>
> >>because the condition (i >= 0) will always be true.
> >>
> >>Why not just allow a genvar to be a signed 32-bit quantity?
>
> True enough, the above example would not work. The genvar definition cannot
> be changed at this time since the IEEE ballot has already been cast (in
> concrete ;-) and the IEEE-2001 document should be available anytime
> between now and September.
>
> As I recall, the positive integer restriction was required by some of the
> vendors to avoid situations where modules might be instantiated with
> negative index ranges. The tool-users on the Behavioral Task Force went out
> of their way to make sure that vendors could implement generate statements
> without weird side-effects that might cause vendors to reject the
> much-requested generate statements.
>
> Your question raises two interesting questions:
>
> Does Cadence permit negative index ranges on arrays of instance? This might
> actually be an omission in the IEEE documentation, where we should have
> required positive index ranges on arrays of instance, too.
>
> Do you know if Cadence's VHDL simulator permits negative index ranges on
> VHDL generate statements and instances?
>
> >>BTW, is there an official place to send LRM errata?
>
> No official place has been set up. For now, why don't you send them to me
> and I will try to at least make a Verilog-2001 directory on my web site to
> store "Submitted_Errata" and "ERRATA"
>
> >>Paul
>
> Regards - Cliff
>
> //*****************************************************************//
> // Cliff Cummings Phone: 503-641-8446 //
> // Sunburst Design, Inc. FAX: 503-641-8486 //
> // 14314 SW Allen Blvd. E-mail: cliffc@sunburst-design.com //
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> // Beaverton, OR 97005 //
> // //
> // Expert Verilog, Synthesis and Verification Training //
> //*****************************************************************//
J. Bhasker
Cadence Design Systems
7535 Windsor Drive, Suite A200, Allentown, PA 18195
610.398.6312, 610.530.7985 (fax), jbhasker@cadence.com
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