From: Paul Graham (pgraham@cadence.com)
Date: Fri Jun 22 2001 - 06:53:02 PDT
Precedence: bulk
> Could you be more specific? Which examples? I believe we determined that 0
> is part of the positive integer space, so at first glance, I did not find
> any of the examples that violated this rule.
Actually, positive means > 0, negative means < 0, and natural means >= 0.
(For reference see the VHDL definitions of subtypes NATURAL and POSITIVE in
package STANDARD.) Given this widely accepted definition, many of the
examples violate the rule about a genvar being positive.
> True enough, the above example would not work. The genvar definition cannot
> be changed at this time since the IEEE ballot has already been cast (in
> concrete ;-) and the IEEE-2001 document should be available anytime
> between now and September.
Nevertheless, I suspect that vendors will implement their own dialects of
verilog. The standard undoubtedly has errors (see positive vs. natural
above) and vendors will not feel constrained to follow a part of the standard
which does not make sense.
> As I recall, the positive integer restriction was required by some of the
> vendors to avoid situations where modules might be instantiated with
> negative index ranges. The tool-users on the Behavioral Task Force went out
> of their way to make sure that vendors could implement generate statements
> without weird side-effects that might cause vendors to reject the
> much-requested generate statements.
I wonder what the side-effects are? The only one I could think of is that
you might not want a hierarchical identifier to have a minus sign:
defparam u1.u2.g[-3].u3.p = 1;
But is this so hard to parse? And if the '-' causes problems, what about
the '[' and ']' characters? And could these problems not be worked around
using substitution characters (like 'n' for '-')?
> Your question raises two interesting questions:
>
> Does Cadence permit negative index ranges on arrays of instance? This might
> actually be an omission in the IEEE documentation, where we should have
> required positive index ranges on arrays of instance, too.
Yes, but I'm not sure how hierarchical naming works. I'll see if I can find
out.
> Do you know if Cadence's VHDL simulator permits negative index ranges on
> VHDL generate statements and instances?
Yes, and hierarchical naming (such as it is in vhdl) poses no problem. If a
for generate has a label 'g', then each iteration of the for generate can be
referred to by 'g(i)', where i is the value of the iterator. I think this
only comes up for block configurations:
for g(-2)
for inst : my_and use entity ...
end for;
end for;
for g(-1 to 3) ...
Paul
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