From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Fri Jun 22 2001 - 13:38:13 PDT
Precedence: bulk
At 06:53 AM 6/22/01 -0700, you wrote:
>> Could you be more specific? Which examples? I believe we determined that 0
>> is part of the positive integer space, so at first glance, I did not find
>> any of the examples that violated this rule.
>
>Actually, positive means > 0, negative means < 0, and natural means >= 0.
>(For reference see the VHDL definitions of subtypes NATURAL and POSITIVE in
>package STANDARD.) Given this widely accepted definition, many of the
>examples violate the rule about a genvar being positive.
Unfortunately I disagree with the "widely accepted definition" claim. To
make sure I was not complete ancient, I looked for "natural" in my Java and
even my old college Ada text. No such definition exists in either of these
languages that I could find. I believe this is a term that was invented for
VHDL. I equate positive to be >= 0, positive, non-zero to be >0, with
similar definitions on the negative side. The Verilog standard has never
had a definition for "natural" nor do I see a compelling reason to add one
to the IEEE document.
>> True enough, the above example would not work. The genvar definition cannot
>> be changed at this time since the IEEE ballot has already been cast (in
>> concrete ;-) and the IEEE-2001 document should be available anytime
>> between now and September.
>
>Nevertheless, I suspect that vendors will implement their own dialects of
>verilog. The standard undoubtedly has errors (see positive vs. natural
>above) and vendors will not feel constrained to follow a part of the standard
>which does not make sense.
Could be true. Vendors that implement an intelligent superset frequently
set a de facto standard that we use as a basis for the next IEEE revision.
$sdf_annotate was not part of the 1995 standard, but all vendors honored
the command so it was added to the 2001 standard.
As a standards group, we heavily restricted generate statements to satisfy
vendor concerns. Cadence was one of the loudest opponents to generate
features so you might not have to look very far to find the party
responsible for limiting negative indexes.
>> As I recall, the positive integer restriction was required by some of the
>> vendors to avoid situations where modules might be instantiated with
>> negative index ranges. The tool-users on the Behavioral Task Force went out
>> of their way to make sure that vendors could implement generate statements
>> without weird side-effects that might cause vendors to reject the
>> much-requested generate statements.
>
>I wonder what the side-effects are? The only one I could think of is that
>you might not want a hierarchical identifier to have a minus sign:
>
> defparam u1.u2.g[-3].u3.p = 1;
>
>But is this so hard to parse? And if the '-' causes problems, what about
>the '[' and ']' characters? And could these problems not be worked around
>using substitution characters (like 'n' for '-')?
I don't think parsing was an issue. I think aesthetics (negative indexes on
an instance name) was more the issue. If Cadence has implemented negative
indexes on an instance array, and if users find creative and powerful ways
to take advantage of them, great! We will update the standard to make this
more explicitly accepted in the next version.
>> Your question raises two interesting questions:
>>
>> Does Cadence permit negative index ranges on arrays of instance? This might
>> actually be an omission in the IEEE documentation, where we should have
>> required positive index ranges on arrays of instance, too.
>
>Yes, but I'm not sure how hierarchical naming works. I'll see if I can find
>out.
>
>> Do you know if Cadence's VHDL simulator permits negative index ranges on
>> VHDL generate statements and instances?
>
>Yes, and hierarchical naming (such as it is in vhdl) poses no problem. If a
>for generate has a label 'g', then each iteration of the for generate can be
>referred to by 'g(i)', where i is the value of the iterator. I think this
>only comes up for block configurations:
>
> for g(-2)
> for inst : my_and use entity ...
> end for;
> end for;
>
> for g(-1 to 3) ...
>
>Paul
Interesting stuff!
Regards - Cliff
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