Not sure how Verilog 2000 widening sign extension work

From: Pragmatic C Software (sjmeyer@pragmatic-c.com)
Date: Thu Jul 05 2001 - 12:52:26 PDT

Precedence: bulk

I amd not sure how expression rules apply to this example. As I read
new Verilog 2000 LRM A has value 5'b01111, then '-' is applied to value
producing 5'b10001 then result is widened to 6'b010001, but I think XL produces
6'b110001. I am not sure if XL applies '-' to value of 6'b001111 or if
there is an implied signed keyword somewhere. Also I am not sure what
effect of signed keyword on A and/or out would be.
/Steve

----------------
`timescale 1ns/1ps
 
module test (out);
      
  output [5:0] out;
    
  wire [4:0] A;
  wire [5:0] out;

    assign A = 15; // = 01111 msb = code bit
    assign out = -A;

    initial
       begin
         $monitor($stime,, "A=%b, out=%b", A, out);
       end

endmodule 

-- 
Steve Meyer
sjmeyer@pragmatic-c.com

This archive was generated by hypermail 2.1.4 : Mon Jul 08 2002 - 12:54:40 PDT and
sponsored by Boyd Technology, Inc.