From: Jayaram Bhasker (jbhasker@cadence.com)
Date: Mon Jul 09 2001 - 12:43:34 PDT
Shalom:
I am curious.
Is Verilog-XL thinking that the parameter in a function
is interpreted as if it appears in the enclosing module?
What if there are two functions with the same parameter declaration within
it?
If not, how is the hierarchical name for the parameter in the function
specified in a defparam statement?
- bhasker
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> From: Shalom Bresticker <shalom@msil.sps.mot.com>
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> To: Paul Graham <pgraham>
> cc: "Shalom Bresticker (r50386)" <r50386@email.sps.mot.com>,
cliffc@mail.sunburst-design.com, btf@boyd.com
> Subject: Re: localparam vs. parameter in subprogram
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> Yes, at least in Verilog-XL. I tried it.
>
> --
> **************************************************************************
> Shalom Bresticker Shalom.Bresticker@motorola.com
> Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
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>
> On Thu, 28 Jun 2001, Paul Graham wrote:
>
> > Date: Thu, 28 Jun 2001 09:03:20 -0700 (PDT)
> > From: Paul Graham <pgraham@cadence.com>
> > To: "Shalom Bresticker (r50386)" <r50386@email.sps.mot.com>
> > Cc: cliffc@mail.sunburst-design.com, btf@boyd.com
> > Subject: Re: localparam vs. parameter in subprogram
> >
> > >
> > > A regular parameter may be redefined by a defparam statement.
> > > A localparam may not.
> >
> > Does this apply to functions and tasks? That is, can a defparam apply
> > to a parameter defined in a function or task?
> >
> > Paul
> >
>
J. Bhasker
Cadence Design Systems
7535 Windsor Drive, Suite A200, Allentown, PA 18195
610.398.6312, 610.530.7985 (fax), jbhasker@cadence.com
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