From: Paul Graham (pgraham@cadence.com)
Date: Tue Jul 10 2001 - 08:03:39 PDT
> But on the other hand, the following could be OK:
>
> for (i=0; i<=1; i=i+1)
> begin
> u[i].j = 3 ;
> end
Good point. Now a module looks a lot like a vhdl record type, and you've
just coded an array of records.
But verilog-xl disallows it, so by definition it's illegal :-)
Error! Instance array index expression must be constant [Verilog-NCAIE]
"test_inst.v", 11: u[i].j
Anyway, it does seem like an undefined area in the language.
Paul
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