From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Tue Jul 10 2001 - 08:10:07 PDT
Paul Graham wrote:
> > But on the other hand, the following could be OK:
> >
> > for (i=0; i<=1; i=i+1)
> > begin
> > u[i].j = 3 ;
> > end
>
> Good point. Now a module looks a lot like a vhdl record type, and you've
> just coded an array of records.
>
> But verilog-xl disallows it, so by definition it's illegal :-)
Aahh, but we're talking about Verilog-2001 !
The 1995 version did not allow variable part-selects either.
>
>
> Error! Instance array index expression must be constant [Verilog-NCAIE]
> "test_inst.v", 11: u[i].j
>
> Anyway, it does seem like an undefined area in the language.
Agreed.
<p>
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