From: Paul Graham (pgraham@cadence.com)
Date: Thu Jul 19 2001 - 12:45:23 PDT
> This would be even worse when generate-if was implemented, since a name
> could reference completely different kinds of objects in different instances.
> For example, instance[1].foo could be a reg, while instance[2].foo could
> be a task, and instance[3].foo could be a module instance.
This is not a problem for VHDL, since there is no else clause in an if
generate, and there is also no case generate, and also every generate
statement must have a label. So a generate statement can be completely
specified by 1) its label, and optionally 2) the index or range of indices
in a for generate. For verilog there would need to be a way of specifying
whether the if or the else clause of a generate was taken, or which branch
of case generate was selected.
Paul
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