From: Michael McNamara (mac@verisity.com)
Date: Thu Jul 19 2001 - 13:41:14 PDT
Steven Sharp writes:
> Precedence: bulk
>
> >>
> >> That's far too vague. For instance, an array of regs can be referenced
> >> using a variable index. Surely this is not allowed for an array of
> >> instances.
> >
> >Why not ?
>
> All references in Verilog must have a bit length known at compile time.
> This is not a problem with a variable index into an array of regs, since
> all of the elements have the same bit width. However, objects in different
> elements of an array of modules can have different bit widths, since they
> can be declared using parameters which are subject to parameter overrides.
> Therefore, a reference to an object in an array of instances using a
> variable index would not have a constant known width.
>
> This would be even worse when generate-if was implemented, since a name
> could reference completely different kinds of objects in different instances.
> For example, instance[1].foo could be a reg, while instance[2].foo could
> be a task, and instance[3].foo could be a module instance.
>
> Steven Sharp
> sharp@cadence.com
<p>Just trying at add clarity here; today with Verilog we do have to
handle the case where a particular reference is of different widths
when instantiated at different times, as shown in the example below,
where foo's reference to bar.this is in one instance a 64 wide real;
and at another instance a 9 bit wide reg.
Of course as Steve implies, because the width of top.ga.pa.this and of
top.gb.pa.this are both known at compile time, there is not a problem
(just a serious amount of coding for the poor compiler writers).
module foo(a,b,c);
output [31:0]a,b;
input [31:0] c;
assign a = c + bar.this;
assign b = c - bar.that;
endmodule
module parent_a;
wire [31:0] a,b;
reg [31:0] c;
initial c = 10000;
foo f1(a,b,c);
initial #10 $display("%m",,a,,b,,c);
endmodule
module parent_b;
wire [31:0] a,b;
reg [31:0] c;
initial c = 20000;
foo f1(a,b,c);
initial #10 $display("%m",,a,,b,,c);
endmodule
module grandparent_a;
parent_a pa();
bar1 bar();
endmodule
module grandparent_b;
parent_b pa();
bar2 bar();
endmodule
module bar1();
real this;
reg [31:0] that;
initial this = 2048.0;
initial that = 1024;
endmodule
module bar2();
reg [8:0] this;
reg [8:0] that;
initial this = 10;
initial that = 100;
endmodule // bar2
module top;
grandparent_a ga();
grandparent_b gb();
endmodule // top
So the question is what is the width of
top.ga[i].pa.this?
(imagining that ga is an array of module instances)
The answer has a return question is, when are you asking?
If i is a genvar, (or parameter) whose value is known at compile time,
than yes 1364-2001 can and should allow one to use the above
statement, as in:
generate
for (i = 0; i < 10; i = i + 1) begin
always @(top.ga[i].pa.this)
$display($time,, "top.ga[%d].pa.this: %h", i, top.ga[i].pa.this);
end
endgenerate
If i is a register variable, whose value varys at run time, then the
above statement is (I believe!) and should be illegal in 1364-2001, as
in:
initial begin: b1
reg [31:0] i;
for (i = 0; i < 10; i = i + 1) begin
$display($time,, "top.ga[%d].pa.this: %h",
i,
top.ga[i].pa.this // illegal use of a variable in a module array reference
);
end
end
--
//' Michael McNamara <mac@verisity.com>
_ // Sr VP Technology 650-934-6888
\ // Verisity Design 650-934-6801 FAX
\// <http://www.verisity.com> 408-930-6875 Cell
--------------------------------------------------------------
Get my verilog emacs mode from <http://www.verilog.com>
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:54:42 PDT
and
sponsored by Boyd Technology, Inc.