From: Paul Graham (pgraham@cadence.com)
Date: Tue Jul 24 2001 - 20:31:44 PDT
Looking at Stuart Sutherland's Verilog-2000 presentation, I see a section
called "Default Nets with Continuous Assigns". It says there that if the
target of a continuous assignment is an undeclared name, then an implicit
wire declaration of the appropriate width will be created. I don't see
any reference to this rule in the LRM itself. Am I missing something?
Paul
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