From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Mon Jul 30 2001 - 05:44:01 PDT
Paul,
I think you are half right.
Section 6.1.2 says,
"The continuous assignment statement shall place a continuous assignment on a net data type. The net may be explicitly declared, or
may inherit an implicit declaration in accordance with the implicit declarations rules defined in 3.5."
Unfortunately, section 3.5 does not mention that case.
I'll file a bug report.
What should the width be in that case ?
According to my mail archives, it seems that a scalar is created unless the name is connected to a vector port.
Shalom
<p>Paul Graham wrote:
> Looking at Stuart Sutherland's Verilog-2000 presentation, I see a section
> called "Default Nets with Continuous Assigns". It says there that if the
> target of a continuous assignment is an undeclared name, then an implicit
> wire declaration of the appropriate width will be created. I don't see
> any reference to this rule in the LRM itself. Am I missing something?
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