From: Paul Graham (pgraham@cadence.com)
Date: Tue Jul 31 2001 - 11:36:04 PDT
>Number: 9
>Category: pending
>Originator: Paul Graham <pgraham@cadence.com>
>Description:
Having experimented with Verilog simulators, I have come to the conclusion
that truncation on the msb side occurs when an expression is assigned to a
smaller target. For instance:
<p> wire [7:0] x = 16'habcd;
<p>In this case, the 8 most significant bits are truncated from the expression,
and only 8'hcd is assigned to x.
<p>Perhaps this behavior can be defined in the LRM, probably somewhere in
chapter 6.
<p>Paul
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