From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Fri Aug 17 2001 - 03:10:00 PDT
The following reply was made to PR errata/16; it has been noted by GNATS.
From: Stuart Sutherland <stuart@sutherland-hdl.com>
To: btf-bugs@boyd.com
Cc:
Subject: Re: errata/16: 19.7 `line - meaning of level parameter is
unclear
Date: Fri, 17 Aug 2001 03:11:34 -0700
I guess I'll add my $0.02 to this topic. It seems to me that we are
carrying the comparison between Verilog and C too far on this. C doesn't
have simulation data structures with complex hierarchy and multiple
instances of the same module. C doesn't have a PLI, either.
`line is not an INPUT to a preprocessor; it is an OUTPUT of a preprocessor
and an INPUT to Verilog tools such as simulation. The engineer writing
Verilog models should never have a need to type in the `line
directive. The engineer writes regular Verilog code. A preprocessor
modifies the code in some way, and adds the `line directives to indicate
original source information. The Verilog simulator could care less what
values are in the `line directives, but it does store the information in
its data structure. Why? because the PLI can access the information, and
use it to relate simulation objects back to original source file. It goes
beyond having more intelligent error messages. Applications such as source
code debuggers and code coverage need to closely link original file
locations with specific simulation data structure objects. Without `line,
the only information available to the PLI would be file and line
information from the results of the preprocessor instead of the original
source information.
Sure, the file is a string that could hold anything, whether sensible or
not. Whatever is in the string, the PLI can access and print out. It
doesn't matter to the PLI or any other tool printing the string whether or
not the string is meaningful. If an engineer were typing in the `line
directive, I would expect some stupid strings to be created. But, a
preprocessor is creating the `line directive. I have great confidence that
whoever wrote the preprocessor is smart enough to use the string
intelligently. Same thing for the level value. It's not an input to a
preprocessor, it's an output. I'm confident a preprocessor will put
something sensible in the field.
Just my thoughts...
Stu
At 02:10 AM 8/17/2001, Shalom Bresticker wrote:
>Precedence: bulk
>
>The following reply was made to PR errata/16; it has been noted by GNATS.
>
>From: Shalom Bresticker <shalom@msil.sps.mot.com>
>To: btf-bugs@boyd.com
>Cc:
>Subject: Re: errata/16: 19.7 `line - meaning of level parameter is unclear
>Date: Fri, 17 Aug 2001 12:05:05 +0300 (IDT)
>
> On Thu, 16 Aug 2001, Dennis Marsa wrote:
>
> > > > Since this directive was envisioned to be used by a
> > > > source code generator (preprocessor, source to source translator,
> etc.)
> > > > the requirement of the parameters was not considered a hardcase.
> You are
> > > > correct, it is not controlling anything; nor would you want it to.
> > >
> > > Again, it looks to me to be a confusion between a compiler DIRECTIVE,
> > > which TELLS the compiler to DO something, on the one hand,
> > > and an informative preprocessor output on the other.
> >
> > But it is a directive. A tool must update its current file/linenumber
> > state upon seeing a `line directive with the info it provides.
>
> I was referring to 'level'.
>
>
> >
> > > If, for CPP, 'linenum' and "filename" were enough, why does Verilog
> need 'level' as well ?
> > > What does it add ? Why can't it just be a comment ?
> >
> > It would seem to me, one application of the level information would be
> > to keep track of all currently active source files on a stack, so that
> when
> > you issue a message you could provide a trail of include files:
> >
> > Error: You messed up! at file: XXX line: YYY
> > included from file: XXX line: YYY
> > included from file: XXX line: YYY
> > ...
> >
> > The level number would guide you whether to push/pop or leave your
> stack alone.
>
> So that's fine as a preprocessor output, not a preprocessor input.
>
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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