From: Paul Graham (pgraham@cadence.com)
Date: Fri Sep 28 2001 - 07:01:29 PDT
Precedence: bulk
> It's not a problem, Paul.
>
> Similarly, "<=" can be "less than or equals" or a nonblocking assignment.
>
> It all depends on context.
>
> Verilog has a context-dependent grammar.
I don't think you understand what I mean. A compiler consists of two
more-or-less independent parts, a lexer and a parser. The lexer groups text
into tokens, and the parser fits tokens in a grammar. Normally, a token can
be identified in isolation. If a verilog lexer sees the string "<=" it will
return the same token always. The parser will interpret is as less than or
equals or nonblocking assignment depending on the context. But the string
"(*" cannot be understood in isolation.
This is similar to an example from C:
int x, y, *z;
x = y/*z;
Now does "/*" mean the start of a comment, or a division followed by a
pointer dereference? It turns out that it is a comment, since comments must
be scanned before any tokens. However, if C did not require comments to be
scanned before tokens, that is, if comments were part of the C grammar (as
opposed to being part of the preprocessor grammar) then the lexer would have
a problem.
A somewhat similar case is in VHDL where the "'" character can either be a
single token (used only in attribute names or qualified expressions) or the
start of a character literal like "'0'". In VHDL the grammar guarantees
that the "'" in an attribute name or qualified expression can never occur in
the same context as a character literal. Still, the parser must provide
feedback to the lexer to handle this case. So the string "bit'('0')" can be
parsed in vhdl without ambiguity.
Likewise in Verilog it appears that an attribute cannot occur immediately
after the '@' token, so the construct "@(*)" can be unambiguously tokenized
as "@", "(", "*", ")".
I just wonder whether this lexical ambiguity was previously taken into
account when attributes and implicit event expressions were introduced.
Paul
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