From: Shalom Bresticker (shalom@msil.sps.mot.com)
Date: Fri Sep 28 2001 - 02:35:38 PDT
Precedence: bulk
It's not a problem, Paul.
Similarly, "<=" can be "less than or equals" or a nonblocking assignment.
It all depends on context.
Verilog has a context-dependent grammar.
-- ************************************************************************** Shalom Bresticker Shalom.Bresticker@motorola.com Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268 P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522890 **************************************************************************On Wed, 26 Sep 2001, Paul Graham wrote:
> Date: Wed, 26 Sep 2001 12:40:00 -0700 (PDT) > From: Paul Graham <pgraham@cadence.com> > To: btf@boyd.com > Subject: amusing grammar ambiguity > > Precedence: bulk > > I just noticed that grammatically, or lexically, speaking, the string "(*" > can either be the start of a verilog-2000 attribute, or an element in an > implicit event control: > > (* case parallel *) > > always @(*) > > This shouldn't be a problem for tools, but I thought it was kind of amusing. > > Paul >
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