From: Paul Graham (pgraham@cadence.com)
Date: Wed Oct 03 2001 - 07:48:08 PDT
Precedence: bulk
> There are separate syntaxes for scalar net declarations and vector net
> declarations. The scalar net declaration also allows you to use the
> "signed" keyword even though that syntax is only for scalars.
That is a general problem with the LRM. There is lots of redundancy in the
language description. Often the same rule is repeated, again and again,
redundantly, in many different places, more often than necessary.
Redundancy is not only aesthetically unappealing, it also leads to bugs in
the description. One such bug shows up in the rules for equality operators,
where it says:
These four operators compare operands bit for bit, with zero filling if
the two operands are of unequal bit length.
The comment about zero filling is a redundant duplication of the general
rule for operand sizing. Before the signed datatype was added to the
language, this was a harmless redundancy. Now it is wrong. If you're
comparing two signed operands of unequal length, of course you don't
zero-fill the shorter operand, you sign-extend it.
The same error also occurs in the section on relational operators. It
wouldn't surprise me if it occurred elsewhere in the LRM.
But getting to your question:
> My question is, what is the meaning of a signed one-bit variable, i.e.,
> sign bit only, without magnitude ?
A 1-bit signed quantity can be thought of as an integer having the range
-1..0. The equivalent vhdl declaration would be:
type one_bit_int is range -1 to 0;
This type would be synthesized using just one bit.
In my opinion this is not a very useful type. For instance, while an
unsigned bit can be used as the carry-in operand to an adder, a signed bit
cannot, since it represents a negative value. Although I suppose you could
have:
module adder(a, b, ci, s);
input [7:0] a, b;
input signed ci;
output [7:0] s;
assign s = a + b - ci;
endmodule
This could be interpreted as an adder with carry-in.
Paul
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