From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Fri Oct 05 2001 - 18:10:01 PDT
Precedence: bulk
The following reply was made to PR errata/11; it has been noted by GNATS.
From: "Clifford E. Cummings" <cliffc@sunburst-design.com>
To: btf-bugs@boyd.com
Cc:
Subject: Re: errata/11: : 12.1.3.4 Example 8: typos and other problems
Date: Fri, 05 Oct 2001 18:04:38 -0700
Shalom is (of course!) right.
This example is full of bugs (never tested because we didn't have a V2K1
simulator).
I will comment on each of the items Shalom has mentioned in-line with his
comments.
I have attached at the bottom of the file, a proposed replacement to this
example. It still is probably not perfect, because as Shalom pointed out,
we don't have the low-level RAM models to fully understand the
functionality. Included in the example are both V2K1 and V95 versions of
the model, plus a couple of RAM wrapper models to make sure the syntax
could at least be compiled.
I don't remember if Adam Krolnik or Kurt Baty or someone else submitted
this example, but if the responsible party has an example of the RAMs that
are supposed to be instantiated, further refinements to the example could
be made.
Nice snooping, Shalom! You missed that the model had port declarations but
no ports (so did I until I tried to compile it). And there is another
subtle error in the second RAM instantiation related to the connection to
the .dqi(data[8+8*i:8*i]) port. The equation should be [7+8*i:8*i].
Comments below.
Regards - Cliff
At 12:30 PM 8/6/01 +0000, you wrote:
>Precedence: bulk
>
>
>
> >Number: 11
> >Category: errata
> >Originator: Shalom Bresticker <Shalom.Bresticker@motorola.com>
> >Description:
>
>
>--------------54390105EBA79A75EAF1D283
>Content-Type: text/plain; charset=us-ascii
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>
>I look at Example 8 in Section 12.1.3.4 and see a lot of things I don't
>understand or seem not 100% correct.
>
>It's mostly a lot of little picky stuff, but still ...
>
>Let's start with what I'm more or less sure of:
>
>- In the instantiation of sms_16b216t0, "...rasb" should be ".rasb",
>"...dqi" should be ".dqi".
>- In the instantiation of sms_16b208t0, "...rasb" should be ".rasb",
>"...dev_id" should be ".dev_id".
Yes - they should all be fixed. We don't want to introduce the ...() port
connection syntax ;-)
>- In the instantiation of sms_16b208t0, i should run from 0 to 7.
Also true. Corrected
>I'm less sure of the rest, since I am not familiar with DIMMs.
>The example seems to be incomplete, which I do not like.
>I think examples in standards documents should contain all needed details.
>
>Adam, I think these examples originated with you.
>Can you check these details ? Thanks.
I agree, it would be nice to have the remaining pieces, but I don't think
that is going to happen.
>- input adr is [11:0], but only [10:0] are used in both instantiations.
I agree. To make the model plausible, I reduce the declaration range to [10:0]
>- input ds[7:0] is not used at all.
Agreed. I deleted it.
>- Is clk really [3:0] ?
Perhaps, but if so, then the instantiations are connecting a 4-bit bus to
what appears to be a 1-bit port. I removed the range declarations on clk.
>- wires rasb, casb, csb, web, bex[7:0] are not used at all.
Agreed. Deleted.
>- The 8M 16b wide mem is called sms_16b216t0,
>while the 16M 8b wide mem is called sms_16b208t0.
>Is that correct? What's the naming convention ?
Who knows what the naming convention is. I agree that it looks funny, but
in the late 1980's, Xilinx put out the XC2064 and the XC2012 devices. The
XC2064 had 64 CLB cells and the XC2012 ({201 , 00} or 20100) had 100 CLB
cells. Since I don't know what the naming convention is, I left this unchanged.
>- devid3[4:0] and devid7[4:0] are undeclared.
Agreed. I declared just one devid[4:0] and changed the references to match.
>- The input adr to dimm is 12b wide, whereas the input address to task
>read_mem is 32b wide.
Again, it looks funny, but since I don't know the intent, I left it unchanged.
>- Task read_mem appears to call a task with the same name which is
>apparently defined within the sms modules, but not shown. The use
>of the same task name for both is confusing.
This actually does not bother me that much. I left it unchanged.
Again, nice snooping! I'm glad someone is closely reading the spec!
>--
>**************************************************************************
>Shalom Bresticker Shalom.Bresticker@motorola.com
>Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
>P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522890
>**************************************************************************
`ifdef V2K1
module dimm (adr, ba, rasx, casx, csx, wex, dqm, cke, data, clk, dev_id);
parameter [31:0] MEM_SIZE = 8, // in mbytes
MEM_WIDTH = 16;
input [10:0] adr;
input ba;
input rasx, casx, csx, wex;
input [ 7:0] dqm;
input cke;
inout [63:0] data;
input clk;
input [ 4:0] dev_id;
genvar i;
generate
case ({MEM_SIZE, MEM_WIDTH})
{32'd8, 32'd16}: // 8Meg x 16 bits wide.
begin
// The generated instance names are word[3].p, word[2].p,
// word[1].p, word[0].p, and the task read_mem
for (i=0; i<4; i=i+1) begin:word
sms_16b216t0 p (.clk(clk), .csb(csx), .cke(cke),
.ba(ba[0]), .addr(adr[10:0]), .rasb(rasx),
.casb(casx), .web(wex), .udqm(dqm[2*i+1]),
.ldqm(dqm[2*i]), .dqi(data[15+16*i:16*i]),
.dev_id(dev_id[4:0]));
end
task read_mem;
input [31:0] address;
output [63:0] data;
begin
word[3].p.read_mem(address, data[63:48]);
word[2].p.read_mem(address, data[47:32]);
word[1].p.read_mem(address, data[31:16]);
word[0].p.read_mem(address, data[15:0]);
end
endtask
end
{32'd16, 32'd8}: // 16Meg x 8 bits wide.
begin
// The generated instance names are byte[7].p, byte[6].p,
// byte[5].p, byte[4].p, byte[3].p, byte[2].p, byte[1].p,
// byte[0].p and the task read_mem
for (i=0; i<8; i=i+1) begin:byte
sms_16b208t0 p (.clk(clk), .csb(csx), .cke(cke),
.ba(ba[0]), .addr(adr[10:0]), .rasb(rasx),
.casb(casx), .web(wex), .dqm(dqm[i]),
.dqi(data[7+8*i:8*i]),.dev_id(dev_id[4:0]));
end
task read_mem;
input [31:0] address;
output [63:0] data;
begin
byte[7].p.read_mem(address, data[63:56]);
byte[6].p.read_mem(address, data[55:48]);
byte[5].p.read_mem(address, data[47:40]);
byte[4].p.read_mem(address, data[39:32]);
byte[3].p.read_mem(address, data[31:24]);
byte[2].p.read_mem(address, data[23:16]);
byte[1].p.read_mem(address, data[15:8]);
byte[0].p.read_mem(address, data[7:0]);
end
endtask
end
// Other memory cases ...
endcase
endgenerate
endmodule
`else
module dimm (adr, ba, rasx, casx, csx, wex, dqm, cke, data, clk, dev_id);
parameter [31:0] MEM_SIZE = 8, // in mbytes
MEM_WIDTH = 16;
input [10:0] adr;
input ba;
input rasx, casx, csx, wex;
input [ 7:0] dqm;
input cke;
inout [63:0] data;
input clk;
input [ 4:0] dev_id;
//genvar i;
//generate
//case ({MEM_SIZE, MEM_WIDTH})
//{32'd8, 32'd16}: // 8Meg x 16 bits wide.
//begin
// The generated instance names are word[3].p, word[2].p,
// word[1].p, word[0].p, and the task read_mem
sms_16b216t0 word3_p (.clk(clk), .csb(csx), .cke(cke), .ba(ba),
.addr(adr[10:0]), .rasb(rasx), .casb(casx), .web(wex), .udqm(dqm[7]),
.ldqm(dqm[6]), .dqi(data[63:48]), .dev_id(dev_id[4:0]));
sms_16b216t0 word2_p (.clk(clk), .csb(csx), .cke(cke), .ba(ba),
.addr(adr[10:0]), .rasb(rasx), .casb(casx), .web(wex), .udqm(dqm[5]),
.ldqm(dqm[4]), .dqi(data[47:32]), .dev_id(dev_id[4:0]));
sms_16b216t0 word1_p (.clk(clk), .csb(csx), .cke(cke), .ba(ba),
.addr(adr[10:0]), .rasb(rasx), .casb(casx), .web(wex), .udqm(dqm[3]),
.ldqm(dqm[2]), .dqi(data[31:16]), .dev_id(dev_id[4:0]));
sms_16b216t0 word0_p (.clk(clk), .csb(csx), .cke(cke), .ba(ba),
.addr(adr[10:0]), .rasb(rasx), .casb(casx), .web(wex), .udqm(dqm[1]),
.ldqm(dqm[0]), .dqi(data[ 15:0]), .dev_id(dev_id[4:0]));
task read_mem1;
input [31:0] address;
output [63:0] data;
begin
word3_p.read_mem(address, data[63:48]);
word2_p.read_mem(address, data[47:32]);
word1_p.read_mem(address, data[31:16]);
word0_p.read_mem(address, data[15:0]);
end
endtask
//end
//{32'd16, 32'd8}: // 16Meg x 8 bits wide.
//begin
// The generated instance names are byte[7].p, byte[6].p,
// byte[5].p, byte[4].p, byte[3].p, byte[2].p, byte[1].p,
// byte[0].p and the task read_mem
sms_16b208t0 byte7_p (.clk(clk), .csb(csx), .cke(cke), .ba(ba),
.addr(adr[10:0]), .rasb(rasx), .casb(casx), .web(wex), .dqm(dqm[7]),
.dqi(data[63:56]),.dev_id(dev_id[4:0]));
sms_16b208t0 byte6_p (.clk(clk), .csb(csx), .cke(cke), .ba(ba),
.addr(adr[10:0]), .rasb(rasx), .casb(casx), .web(wex), .dqm(dqm[6]),
.dqi(data[55:48]),.dev_id(dev_id[4:0]));
sms_16b208t0 byte5_p (.clk(clk), .csb(csx), .cke(cke), .ba(ba),
.addr(adr[10:0]), .rasb(rasx), .casb(casx), .web(wex), .dqm(dqm[5]),
.dqi(data[47:40]),.dev_id(dev_id[4:0]));
sms_16b208t0 byte4_p (.clk(clk), .csb(csx), .cke(cke), .ba(ba),
.addr(adr[10:0]), .rasb(rasx), .casb(casx), .web(wex), .dqm(dqm[4]),
.dqi(data[39:32]),.dev_id(dev_id[4:0]));
sms_16b208t0 byte3_p (.clk(clk), .csb(csx), .cke(cke), .ba(ba),
.addr(adr[10:0]), .rasb(rasx), .casb(casx), .web(wex), .dqm(dqm[3]),
.dqi(data[31:24]),.dev_id(dev_id[4:0]));
sms_16b208t0 byte2_p (.clk(clk), .csb(csx), .cke(cke), .ba(ba),
.addr(adr[10:0]), .rasb(rasx), .casb(casx), .web(wex), .dqm(dqm[2]),
.dqi(data[23:16]),.dev_id(dev_id[4:0]));
sms_16b208t0 byte1_p (.clk(clk), .csb(csx), .cke(cke), .ba(ba),
.addr(adr[10:0]), .rasb(rasx), .casb(casx), .web(wex), .dqm(dqm[1]), .dqi(
data[15:8]),.dev_id(dev_id[4:0]));
sms_16b208t0 byte0_p (.clk(clk), .csb(csx), .cke(cke), .ba(ba),
.addr(adr[10:0]), .rasb(rasx), .casb(casx), .web(wex), .dqm(dqm[0]),
.dqi( data[7:0]),.dev_id(dev_id[4:0]));
task read_mem2;
input [31:0] address;
output [63:0] data;
begin
byte7_p.read_mem(address, data[63:56]);
byte6_p.read_mem(address, data[55:48]);
byte5_p.read_mem(address, data[47:40]);
byte4_p.read_mem(address, data[39:32]);
byte3_p.read_mem(address, data[31:24]);
byte2_p.read_mem(address, data[23:16]);
byte1_p.read_mem(address, data[15:8]);
byte0_p.read_mem(address, data[7:0]);
end
endtask
//end
// Other memory cases ...
//endcase
//endgenerate
endmodule
`endif
module sms_16b216t0 (clk, csb, cke, ba, addr, rasb, casb, web, udqm, ldqm,
dqi, dev_id);
input [10:0] addr;
input ba;
input rasb, casb, csb, web;
input udqm, ldqm;
input cke;
inout [15:0] dqi;
input clk;
input [ 4:0] dev_id;
reg [15:0] mem [0:1023];
task read_mem;
input [10:0] address;
output [15:0] data;
begin
end
endtask
endmodule
module sms_16b208t0 (clk, csb, cke, ba, addr, rasb, casb, web, dqm, dqi,
dev_id);
input [10:0] addr;
input ba;
input rasb, casb, csb, web;
input dqm;
input cke;
inout [ 7:0] dqi;
input clk;
input [ 4:0] dev_id;
reg [15:0] mem [0:1023];
task read_mem;
input [10:0] address;
output [15:0] data;
begin
end
endtask
endmodule
//*****************************************************************//
// Cliff Cummings Phone: 503-641-8446 //
// Sunburst Design, Inc. FAX: 503-641-8486 //
// 14314 SW Allen Blvd. E-mail: cliffc@sunburst-design.com //
// PMB 501 Web: www.sunburst-design.com //
// Beaverton, OR 97005 //
// //
// Expert Verilog, Synthesis and Verification Training //
//*****************************************************************//
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