From: Don Mills (mills@lcdm-eng.com)
Date: Tue Oct 23 2001 - 07:35:40 PDT
Would it be "out of line" to submit an article to EE Times (may via
Richard Goering) to express the committees concerns regarding the
current state of the release? This would be done with the purpose of
educating the public.
Just a thought?
dm
Shalom Bresticker wrote:
> As you can see, the IEEE has officially released 1364-2001.
> While the print version is not yet available, an online PDF version
> is already available.
> I've downloaded it, and it contains NONE of the corrections we
> requested,
> including those we classified as critical.
> Since they messed up the formatting of the bulleted lists as well,
> it even looks pretty bad.
>
> Shalom
>
>
> http://www.eet.com/printableArticle?doc_id=OEG20011018S0085
>
> --
> **************************************************************************
> Shalom Bresticker Shalom.Bresticker@motorola.com
> Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
> P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522890
> **************************************************************************
>
> [Click here!]
> www.cmpnet.com
[EE Times] The Technology Network
>
> Verilog-2001 language ready to roll
> By By Richard Goering , EE Times
> Oct 18, 2001 (1:51 PM)
> URL: http://www.eetimes.com/story/OEG20011018S0085
>
> NAPA, Calif. — Implementation of the new Verilog-2001 hardware
> description language became practical with the IEEE's release
> Wednesday (Oct. 17) of documentation that describes the standard,
> officially known as IEEE 1364-2001. Meanwhile, some EDA vendors are
> quietly moving ahead and adding support for Verilog-2001 constructs.
>
> Although the IEEE approved Verilog-2001 in March, until now only a
> handful of people have had access to working versions of the
> documentation, said Dennis Brophy, chairman of the Accellera
> standards organization. "Now we have the authenticated version from
> the IEEE that's ready for the rest of the industry to use," he said.
>
> Compared to previous versions of the language, Verilog-2001 promises
> to let designers work at a higher level of abstraction, and to
> achieve more timing accuracy for deep-submicron ICs. It also
> promises better simulation control and improved tool
> interoperability through an enhanced programming language interface
> (PLI).
>
> While chip designers have yet to get up to speed on Verilog-2001, a
> few EDA vendors who have been involved in the standard's development
> are already moving ahead. For example, Cadence Design Systems Inc.
> has added some Verilog-2001 constructs to its PKS synthesis and
> NC-Sim simulation tools and will add more based on user demand, a
> spokesman said.
>
> Co-Design Automation Inc. worked in parallel with the Verilog-2001
> effort, and its Systemsim simulator supports Verilog-2001, said
> Simon Davidmann, chief executive officer of Co-Design. Superlog's
> additional language capabilities are "built on the Verilog-2001
> base," he said. Mentor Graphics Corp. has implemented "substantial
> parts" of Verilog-2001 into ModelSim, said Anne Sanquini, vice
> president of Mentor's HDL design division.
>
> Higher models, faster code
>
> Behavioral extensions in Verilog-2001, Brophy said, are aimed at
> letting users create higher-level models and write code faster. He
> said that the addition of "configuration" blocks will allow for
> better design management and that "generate" statements, a concept
> borrowed from VHDL, will help prevent repetitious coding. Other new
> language features include multidimensional arrays, improved file I/O
> and re-entrant tasks.
>
> To support more accurate ASIC and FPGA timing, Verilog-2001 adds
> support for on-detect pulse error propagation, negative pulse
> detection, new timing constraint checks, negative timing constraints
> and enhanced Standard Delay Format (SDF) support. The Verilog Charge
> Dump (VCD) file format has been extended beyond four states to
> support more detail on net strength and port changes.
>
> New features added to the Verilog programming interface (VPI), which
> is part of the PLI, provide improved control over simulation and
> debugging, Brophy said. He also noted that new VPI functions allow
> for better integration of C language models.
>
> The PDF version of the IEEE standard 1364-2001 is available now,
> with the print version coming in late October. These can be ordered
> at www.ieee.org. Meanwhile, consultant Stuart Sutherland has a
> Verilog-2001 FAQ at www.verilog-2001.com. An updated Verilog 2001
> tutorial by Sutherland is available at www.EEdesign.com.
> www.cmpnet.com
[EE Times] The Technology Network
>
> Copyright 1998 CMP Media Inc.
>
>
-- ========================================================== Don Mills LCDM Engineering (Logic, Coding, & Design Methodology) mills@lcdm-eng.com www.lcdm-eng.com 801-282-6560 Office PHONE 801-641-5882 Mobile PHONE 4158 W. Ben Armine Cir., South Jordan, UT 84095-9101 ==========================================================
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