From: Dennis Marsa (drm@xilinx.com)
Date: Tue Oct 23 2001 - 10:41:23 PDT
Precedence: bulk
Adam Krolnik wrote:
>
> Precedence: bulk
>
> Hi Paul;
>
> You are correct - that is old language...
>
> It started out being called the 'line and file' directive.
> the directive `line takes it all in now.
>
> The properties vpiDefLineNo and vpiDefFile are affected by the `line
> directive.
>
> The properties vpiLineNo and vpiFile also should be affected by the
> `line directive, no?!
Section 26.3.3 on page 627 makes the same statement for vpiLineNo
and vpiFile.
> Can anyone explain the difference between these two sets of attributes?
For modules, vpiDefLineNo/vpiDefFile refer to the location of the module
definition; whereas vpiLineNo/vpiFile refer to the location where the module
is instantiated
The exception is if the module is a top-level module, then they both refer
to the location of the module definition.
I don't know if there is explicit language anywhere documenting this, but
this is the behavior I have observed with Verilog-XL and it seems like
a reasonable interpretation.
Dennis Marsa
Xilinx, Inc.
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