From: Paul Graham (pgraham@cadence.com)
Date: Wed Oct 24 2001 - 08:26:22 PDT
Precedence: bulk
> I believe the standard very clealy states that a genvar is only valid at
> elaboration time. It therefore would have no value during simulation time,
> and therefore should not be a legal expression in an attribute.
No, a reference to a genvar results in a value at simulation time.
Otherwise, the following would make no sense:
genvar i;
generate for (i = 0; i < 8; i = i + 1)
begin : blah
assign q[i] = d[i];
end
endgenerate
When the simulator executes, there must be some meaning for q[i] and d[i].
While the genvar data structure may exist only during elaboration, its value
remains for simulation. So it is a perfectly good, simulation-time
constant.
My original question was really to find out whether attributes were intended
to be more like preprocessor-style directives or vhdl attributes.
Preprocessor directives in C support only the simplest of expressions, while
vhdl attributes can have any complex constant value (including calls to
constant functions). It seems the intent is be like vhdl.
I also was wondering how to implement attributes in my parser. If
attributes are simple, preprocessor-like directives, then a simple data
structure holding, say, a string and integer would be sufficient for the
parser to store an attribute's value.
Also, since attributes are intended in part to provide a vendor-independent
way of specifying synthesis directives, I wondered how some commonly used
synthesis directives could be specified using attributes. One very common
directive is:
// ambit synthesis off
...
// ambit synthesis on
Suppose this were translated into an attribute:
(* synthesis = 0 *)
...
(* synthesis = 1 *)
Now suppose that the expression depends on a parameter. Then synthesis
could be enabled or disabled in a module based on some defparam in another
module. Thinking about this gave me a headache.
Paul
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:54:48 PDT
and
sponsored by Boyd Technology, Inc.