From: Daryl Stewart (Daryl.Stewart@cl.cam.ac.uk)
Date: Fri Nov 30 2001 - 09:24:40 PST
Precedence: bulk
> it makes it easier to reason about grammars.
On that subject, can anyone tell me if I'm wrong that the following syntax is
ambiguous:
nonblocking_assignment ::= variable_lvalue <= [ delay_or_event_control ]
expression
delay_or_event_control ::=
delay_control
| event_control
| repeat ( expression ) event_control
delay_control ::=
# delay_value
| # ( mintypmax_expression )
delay_value ::=
unsigned_number
| parameter_identifier
| specparam_identifier
| mintypmax_expression
mintypmax_expression ::=
expression
| expression : expression : expression
There's an ambiguity in the grammar since we can have
variable_lvalue <= # expression expression
so is:
l <= # a | b | c;
equal to:
l <= #(a) ((| b) | c));
or:
l <= #(a | b) (| c);
delay_value used to have constant_mintypmax_expression instead of
mintypmax_expression, which is no better really, and Verilog-XL refuses:
l <= # 1:2:3 e;
and requires:
l <= #(1:2:3) e;
anyway.
delay_value must (?) allow mintypmax_expression for when it is part of a
delay2 or delay3, which is never ambiguously followed by an expression.
One solution is for delay_control to become
delay_control ::=
# unsigned_number
| # parameter_identifier
| # specparam_identifier
| # ( mintypmax_expression )
cheers
Daryl
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