From: Daryl Stewart (Daryl.Stewart@cl.cam.ac.uk)
Date: Mon Dec 03 2001 - 05:02:25 PST
Precedence: bulk
> Sorry, guys.
>
> "The mintypmax expression after a #" definitely does NOT have to be enclosed in parentheses,
> and that goes back to 1364-1995.
>
> Shalom
According to 1364-1995
delay_control ::=
<B>#</B> delay_value
| <B>#</B> <B>(</B> mintypmax_expression <B>)</B>
and
delay_value ::=
unsigned_number
| paramter_identifier
| constant_mintypmax_expression
So even back then you could only have a CONSTANT_mintypmax_expression
unparenthesised.
The grammar required ( and ) around any other mintypmax_expression.
Even so:
> > Verilog-XL refuses:
> > l <= # 1:2:3 e;
despite 1364-1995 allowing it
<p>Now, the CONSTANT requirement is not in the grammar.
<p>This still doesn't answer the question:
> > can anyone tell me if I'm wrong that the following syntax is ambiguous:
As soon as someone proves it wrong I'll shut up, if someone agrees I'll submit
an enhancement and shut up ;)
<p>cheers
Daryl
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:54:48 PDT
and
sponsored by Boyd Technology, Inc.